- remove unused harnessTransforms

-

tapeout/src/main/scala/barstools/tapeout/transforms/GenerateTopAndHarness.scala

@@ -38,14 +38,6 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
   val topAnnos = synTop.map(st => ReParentCircuitAnnotation(rootCircuitTarget.module(st))) ++
     topDotfOut.map(BlackBoxResourceFileNameAnno)
 
-  // order is determined by DependencyAPIMigration
-  val harnessTransforms = Seq(
-    new ConvertToExtMod,
-    new RemoveUnusedModules,
-    new AvoidExtModuleCollisions,
-    new AddSuffixToModuleNames
-  )
-
   // Dump firrtl and annotation files
   protected def dump(
                       circuit: Circuit,
@@ -88,6 +80,7 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
     // Execute top and get list of ExtModules to avoid collisions
     val topExtModules = executeTop()
 
+    // order is determined by DependencyAPIMigration
     val harnessAnnos =
       harnessDotfOut.map(BlackBoxResourceFileNameAnno).toSeq ++
         harnessTop.map(ht => ModuleNameSuffixAnnotation(rootCircuitTarget, s"_in${ht}")) ++

tapeout/src/test/scala/barstools/tapeout/transforms/GenerateSpec.scala

@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package barstools.tapeout.transforms
+
+import chisel3._
+import chisel3.experimental.ExtModule
+import chisel3.stage.ChiselStage
+import firrtl.FileUtils
+import org.scalatest.freespec.AnyFreeSpec
+
+import java.io.{File, PrintWriter}
+
+class BlackBoxInverter extends ExtModule {
+  val in = IO(Input(Bool()))
+  val out = IO(Output(Bool()))
+}
+
+class GenerateExampleModule extends MultiIOModule {
+  val in = IO(Input(Bool()))
+  val out = IO(Output(Bool()))
+
+  val inverter = Module(new BlackBoxInverter)
+  inverter.in := in
+  val inverted = inverter.out
+
+  val reg = RegInit(0.U(8.W))
+  reg := reg + inverted.asUInt
+  out := reg
+}
+
+class ToBeMadeExternal extends MultiIOModule {
+  val in = IO(Input(Bool()))
+  val out = IO(Output(Bool()))
+
+  val reg = RegInit(0.U(8.W))
+  reg := reg + in.asUInt + 2.U
+  out := reg
+}
+
+class GenerateExampleTester extends MultiIOModule {
+  val success = IO(Output(Bool()))
+
+  val  mod = Module(new GenerateExampleModule)
+  mod.in := 1.U
+
+  val  mod2 = Module(new ToBeMadeExternal)
+  mod2.in := 1.U
+
+  val reg = RegInit(0.U(8.W))
+  reg := reg + mod.out + mod2.out
+
+  success := reg === 100.U
+
+  when(reg === 100.U) {
+    stop()
+  }
+}
+
+class GenerateSpec extends AnyFreeSpec {
+  "generate test data" in {
+    val targetDir = "test_run_dir/generate_spec_source"
+    FileUtils.makeDirectory(targetDir)
+
+    val printWriter = new PrintWriter(new File(s"$targetDir/GenerateExampleTester.fir"))
+    printWriter.write((new ChiselStage()).emitFirrtl(new GenerateExampleTester))
+    printWriter.close()
+
+    val blackBoxInverterText = """
+                                 |module BlackBoxInverter(
+                                 |    input  [0:0] in,
+                                 |    output [0:0] out
+                                 |);
+                                 |  assign out = !in;
+                                 |endmodule
+                                 |""".stripMargin
+
+    val printWriter2 = new PrintWriter(new File(s"$targetDir/BlackBoxInverter.v"))
+    printWriter2.write(blackBoxInverterText)
+    printWriter2.close()
+
+
+  }
+
+  "generate top test" in {
+    val sourceDir = "test_run_dir/generate_spec_source"
+    val targetDir = "test_run_dir/generate_spec"
+
+    GenerateTop.main(Array(
+      "-i", s"$sourceDir/GenerateExampleTester.fir",
+      "-o", s"$targetDir/GenerateExampleTester.v"
+    ))
+  }
+}

tapeout/src/test/scala/barstools/tapeout/transforms/GenerateTopSpec.scala

@@ -2,10 +2,11 @@
 
 package barstools.tapeout.transforms
 
+import firrtl.FileUtils
 import org.scalatest.freespec.AnyFreeSpec
 import org.scalatest.matchers.should.Matchers
 
-import java.io.{ByteArrayOutputStream, PrintStream}
+import java.io.{ByteArrayOutputStream, File, PrintStream, PrintWriter}
 
 class GenerateTopSpec extends AnyFreeSpec with Matchers {
   "Generate top and harness" - {
@@ -24,19 +25,45 @@ class GenerateTopSpec extends AnyFreeSpec with Matchers {
   }
 
   "generate harness should " in {
-    val buffer = new ByteArrayOutputStream()
+    val targetDir = "test_run_dir/generate_top_spec"
-    Console.withOut(new PrintStream(buffer)) {
+    FileUtils.makeDirectory(targetDir)
+
+    val stream = getClass.getResourceAsStream("/BlackBoxFloatTester.fir")
+    val input = scala.io.Source.fromInputStream(stream).getLines()
+    val printWriter = new PrintWriter(new File(s"$targetDir/BlackBoxFloatTester.fir"))
+    printWriter.write(input.mkString("\n"))
+    printWriter.close()
+
+    println(s"""Resource: ${input.mkString("\n")}""")
+
+
+//    val buffer = new ByteArrayOutputStream()
+//    Console.withOut(new PrintStream(buffer)) {
       GenerateTopAndHarness.main(
         Array(
           "--target-dir", "test_run_dir/generate_top_spec",
-          "-i", "/Users/chick/Adept/dev/masters/barstools/tapeout/src/test/resources/BlackBoxFloatTester.fir",
+          "-i", s"$targetDir/BlackBoxFloatTester.fir",
-//          "-X", "low",
+          "-o",
-//          "-ll", "info",
+          "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.v",
-//          "--help"
+          "-tho", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.v",
+          "-i", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.fir",
+          "--syn-top", "UnitTestSuite",
+          "--harness-top", "TestHarness",
+          "-faf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.anno.json",
+          "-tsaof", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.anno.json",
+          "-tdf", "firrtl_black_box_resource_files.top.f",
+          "-tsf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.fir",
+          "-thaof", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.anno.json",
+          "-hdf", "firrtl_black_box_resource_files.harness.f",
+          "-thf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.fir",
+          "--infer-rw",
+          "--repl-seq-mem", "-c:TestHarness:-o:chipyard.unittest.TestHarness.IceNetUnitTestConfig.top.mems.conf",
+          "-thconf", "chipyard.unittest.TestHarness.IceNetUnitTestConfig.harness.mems.conf",
+          "-td", "test_run_dir/from-ci",
+          "-ll", "info"
         )
       )
     }
-    val output = buffer.toString
+//    val output = buffer.toString
-    println(output)
+//    println(output)
-  }
 }