Address fpga srcs

fpga/src/main/resources/vcu118/sdboot/Makefile

@@ -10,7 +10,10 @@ CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0
 CFLAGS+= -I $(ROOT_DIR)/include -I.
 LFLAGS=-static -nostdlib -L $(ROOT_DIR)/linker -T sdboot.elf.lds
 
-#PBUS_CLK passed in
+PBUS_CLK ?= 1000000 # default to 1MHz but really should be overridden
+
+default: elf bin dump
+
 elf := $(BUILD_DIR)/sdboot.elf
 $(elf): head.S kprintf.c sd.c
 	mkdir -p $(BUILD_DIR)

fpga/src/main/resources/vcu118/sdboot/include/platform.h

@@ -1,10 +1,9 @@
 // See LICENSE for license details.
 
-#ifndef _EAGLE_PLATFORM_H
+#ifndef _CHIPYARD_PLATFORM_H
-#define _EAGLE_PLATFORM_H
+#define _CHIPYARD_PLATFORM_H
 
 #include "const.h"
-#include "riscv_test_defaults.h"
 #include "devices/clint.h"
 #include "devices/gpio.h"
 #include "devices/plic.h"
@@ -105,4 +104,4 @@
 // Misc
 
 
-#endif /* _SIFIVE_PLATFORM_H */
+#endif /* _CHIPYARD_PLATFORM_H */

fpga/src/main/resources/vcu118/sdboot/include/riscv_test_defaults.h

@@ -1,81 +0,0 @@
-// See LICENSE.Sifive for license details.
-#ifndef _RISCV_TEST_DEFAULTS_H
-#define _RISCV_TEST_DEFAULTS_H
-
-#define TESTNUM x28
-#define TESTBASE 0x4000
-
-#define RVTEST_RV32U \
-  .macro init; \
-  .endm
-
-#define RVTEST_RV64U \
-  .macro init; \
-  .endm
-
-#define RVTEST_RV32UF \
-  .macro init; \
-  /* If FPU exists, initialize FCSR. */ \
-  csrr t0, misa; \
-  andi t0, t0, 1 << ('F' - 'A'); \
-  beqz t0, 1f; \
-  /* Enable FPU if it exists. */ \
-  li t0, MSTATUS_FS; \
-  csrs mstatus, t0; \
-  fssr x0; \
-1: ; \
-  .endm
-
-#define RVTEST_RV64UF \
-  .macro init; \
-  /* If FPU exists, initialize FCSR. */ \
-  csrr t0, misa; \
-  andi t0, t0, 1 << ('F' - 'A'); \
-  beqz t0, 1f; \
-  /* Enable FPU if it exists. */ \
-  li t0, MSTATUS_FS; \
-  csrs mstatus, t0; \
-  fssr x0; \
-1: ; \
-  .endm
-
-#define RVTEST_CODE_BEGIN \
-  .section .text.init; \
-  .globl _prog_start; \
-_prog_start: \
-  init;
-
-#define RVTEST_CODE_END \
-  unimp
-
-#define RVTEST_PASS \
-  fence; \
-  li t0, TESTBASE; \
-  li t1, 0x5555; \
-  sw t1, 0(t0); \
-1: \
-  j 1b;
-
-#define RVTEST_FAIL \
-  li t0, TESTBASE; \
-  li t1, 0x3333; \
-  slli a0, a0, 16; \
-  add a0, a0, t1; \
-  sw a0, 0(t0); \
-1: \
-  j 1b;
-
-#define EXTRA_DATA
-
-#define RVTEST_DATA_BEGIN \
-  EXTRA_DATA \
-  .align 4; .global begin_signature; begin_signature:
-
-#define RVTEST_DATA_END \
-  _msg_init: .asciz "RUN\r\n"; \
-  _msg_pass: .asciz "PASS"; \
-  _msg_fail: .asciz "FAIL "; \
-  _msg_end: .asciz "\r\n"; \
-  .align 4; .global end_signature; end_signature:
-
-#endif /* _RISCV_TEST_DEFAULTS_H */

fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds

@@ -47,7 +47,7 @@ SECTIONS
 
   .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT {
     *(.rodata .rodata.* .gnu.linkonce.r.*)
-    *(.dtb)
+    *(.dtb) /* Must be last if this code is added to RC's BootROM */
   } >bootrom_mem  :data
 
   PROVIDE(_data = ADDR(.rodata));

fpga/src/main/scala/vcu118/Configs.scala

@@ -28,16 +28,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
 class WithSystemModifications extends Config((site, here, up) => {
   case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top
   case DebugModuleKey => None // disable debug module
-  case SystemBusKey => up(SystemBusKey).copy(
+  case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000))
-    errorDevice = Some(DevNullParams(
-      Seq(AddressSet(0x3000, 0xfff)),
-      maxAtomic=site(XLen)/8,
-      maxTransfer=128,
-      region = RegionType.TRACKED)))
-  case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency =
-    Some(BigDecimal(site(FPGAFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt))
-  case ControlBusKey => up(ControlBusKey, site).copy(
-    errorDevice = None)
   case DTSTimebase => BigInt(1000000)
   case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
     // invoke makefile for sdboot

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -41,7 +41,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
   val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
   val ddr2       = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput()))
 
-  val topDesign = LazyModule(p(BuildTop)(dp))
+  val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
 
 // DOC include start: ClockOverlay
   // place all clocks in the shell