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Address fpga srcs

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abejgonzalez
2020-11-12 15:39:29 -08:00
parent 999ae05bfe
commit 55f19f79d3
6 changed files with 10 additions and 98 deletions
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fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -41,7 +41,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
val ddr2 = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput()))
val topDesign = LazyModule(p(BuildTop)(dp))
val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
// DOC include start: ClockOverlay
// place all clocks in the shell