Address fpga srcs

fpga/src/main/scala/vcu118/Configs.scala

@@ -28,16 +28,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
 class WithSystemModifications extends Config((site, here, up) => {
   case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top
   case DebugModuleKey => None // disable debug module
-  case SystemBusKey => up(SystemBusKey).copy(
-    errorDevice = Some(DevNullParams(
-      Seq(AddressSet(0x3000, 0xfff)),
-      maxAtomic=site(XLen)/8,
-      maxTransfer=128,
-      region = RegionType.TRACKED)))
-  case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency =
-    Some(BigDecimal(site(FPGAFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt))
-  case ControlBusKey => up(ControlBusKey, site).copy(
-    errorDevice = None)
+  case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000))
   case DTSTimebase => BigInt(1000000)
   case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
     // invoke makefile for sdboot

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -41,7 +41,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
   val sys_clock2 = Overlay(ClockInputOverlayKey, new SysClock2VCU118ShellPlacer(this, ClockInputShellInput()))
   val ddr2       = Overlay(DDROverlayKey, new DDR2VCU118ShellPlacer(this, DDRShellInput()))
 
-  val topDesign = LazyModule(p(BuildTop)(dp))
+  val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop")
 
 // DOC include start: ClockOverlay
   // place all clocks in the shell