Rename HasCeaseSuccessIO -> HasCeaseIO

generators/chipyard/src/main/scala/Subsystem.scala

@@ -70,11 +70,11 @@ trait CanHaveChosenInDTS { this: BaseSubsystem =>
   }
 }
 
-trait HasCeaseSuccessIO { this: HasTileNotificationSinks =>
-  val success = InModuleBody {
-    val success = IO(Output(Bool()))
-    success := tileCeaseSinkNode.in.head._1.asUInt.andR
-    success
+trait HasCeaseIO { this: HasTileNotificationSinks =>
+  val cease = InModuleBody {
+    val cease = IO(Output(Bool()))
+    cease := tileCeaseSinkNode.in.head._1.asUInt.andR
+    cease
   }
 }
 
@@ -82,7 +82,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
     with InstantiatesHierarchicalElements
     with HasTileNotificationSinks
     with HasTileInputConstants
-    with HasCeaseSuccessIO
+    with HasCeaseIO
     with CanHavePeripheryCLINT
     with CanHavePeripheryPLIC
     with HasPeripheryDebug

generators/chipyard/src/main/scala/iobinders/IOBinders.scala

@@ -33,7 +33,7 @@ import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDevi
 import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
 import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
-import chipyard.{CanHaveMasterTLMemPort, HasCeaseSuccessIO, ChipyardSystem, ChipyardSystemModule}
+import chipyard.{CanHaveMasterTLMemPort, HasCeaseIO, ChipyardSystem, ChipyardSystemModule}
 
 import scala.reflect.{ClassTag}
 
@@ -459,10 +459,10 @@ class WithNICIOPunchthrough extends OverrideIOBinder({
 })
 
 class WithCeasePunchThrough extends OverrideIOBinder({
-  (system: HasCeaseSuccessIO) => {
-    val success: Bool = IO(Output(Bool())).suggestName("success")
-    success := system.success.getWrappedValue
-    (Seq(SuccessPort(() => success)), Nil)
+  (system: HasCeaseIO) => {
+    val cease: Bool = IO(Output(Bool())).suggestName("cease")
+    cease := system.cease.getWrappedValue
+    (Seq(SuccessPort(() => cease)), Nil)
   }
 })