From c27c9d5d1882508640acd86682822a1d4da5e42e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Mar 2021 02:16:18 -0700 Subject: [PATCH 1/5] Add option to add async queues between chip-serialIO and harness serdes --- .../src/main/scala/HarnessBinders.scala | 24 ++++++++++++++----- generators/testchipip | 2 +- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 643b2065..fe03f951 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -238,23 +238,35 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ }) -class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ +class WithSerialAdapterTiedOff(asyncQueue: Boolean = false) extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) + val bits = if (asyncQueue) { + SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) + } else { + port.bits + } + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) SerialAdapter.tieoff(ram.module.io.tsi_ser) }) } }) -class WithSimSerial extends OverrideHarnessBinder({ +class WithSimSerial(asyncQueue: Boolean = false) extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) - val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool) - when (success) { th.success := true.B } + val bits = if (asyncQueue) { + SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) + } else { + port.bits + } + withClockAndReset(th.harnessClock, th.harnessReset) { + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) + val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool) + when (success) { th.success := true.B } + } }) } }) diff --git a/generators/testchipip b/generators/testchipip index 282ca2e2..6e2db28a 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 282ca2e25e191e63051afafc8808561f6a54c695 +Subproject commit 6e2db28a165627f44b6e97d40930406bbfb6e3e3 From 8a78565c04d49ba6d4ccf569009ad0d17ca3fdaf Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Mar 2021 12:45:40 -0700 Subject: [PATCH 2/5] Update BridgeBinders with new HarnessRAM clocking --- generators/firechip/src/main/scala/BridgeBinders.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index bdbb7d44..f0b376d0 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -70,8 +70,9 @@ class WithSerialBridge extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) - SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) + val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) + SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) } Nil } From edd54e776c0cfdc4c5ce2ec129cefd7731a14780 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Mar 2021 14:05:33 -0700 Subject: [PATCH 3/5] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 6e2db28a..ca3cc624 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6e2db28a165627f44b6e97d40930406bbfb6e3e3 +Subproject commit ca3cc6245c2edd253bcec67283dbfdbda4d5c3dc From a013f0d561fb06a1118e3cbf766d734da427a847 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Mar 2021 15:09:29 -0700 Subject: [PATCH 4/5] Fix SerialTL HarnessRAM BridgeBinder --- generators/firechip/src/main/scala/BridgeBinders.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index f0b376d0..95f0bf3b 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -71,7 +71,9 @@ class WithSerialBridge extends OverrideHarnessBinder({ ports.map { port => implicit val p = GetSystemParameters(system) val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) + val ram = withClockAndReset(th.harnessClock, th.harnessReset) { + SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) + } SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) } Nil From c5e7d8a9b2d6f4321a94cc041e51919bb4209973 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Mar 2021 15:35:41 -0700 Subject: [PATCH 5/5] Give HarnessRAM implicit clock/reset in SerialTiedOff --- .../src/main/scala/HarnessBinders.scala | 20 +++++++------------ 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index fe03f951..9159873d 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -238,30 +238,24 @@ class WithTiedOffDebug extends OverrideHarnessBinder({ }) -class WithSerialAdapterTiedOff(asyncQueue: Boolean = false) extends OverrideHarnessBinder({ +class WithSerialAdapterTiedOff extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val bits = if (asyncQueue) { - SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) - } else { - port.bits + val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) + withClockAndReset(th.harnessClock, th.harnessReset) { + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) + SerialAdapter.tieoff(ram.module.io.tsi_ser) } - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) - SerialAdapter.tieoff(ram.module.io.tsi_ser) }) } }) -class WithSimSerial(asyncQueue: Boolean = false) extends OverrideHarnessBinder({ +class WithSimSerial extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { implicit val p = chipyard.iobinders.GetSystemParameters(system) ports.map({ port => - val bits = if (asyncQueue) { - SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) - } else { - port.bits - } + val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) withClockAndReset(th.harnessClock, th.harnessReset) { val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool)