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Fix compile breaking due to merge conflict

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This commit is contained in:
Jerry Zhao
2023-02-02 10:01:35 -08:00
parent e732fdf130
commit 5525cd7571
1 changed files with 5 additions and 0 deletions
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5
generators/chipyard/src/main/scala/SpikeTile.scala
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@@ -58,6 +58,11 @@ case class SpikeCoreParams(
val rasEntries = 0 val rasEntries = 0
val btbEntries = 0 val btbEntries = 0
val bhtEntries = 0 val bhtEntries = 0
val traceHasWdata = false
val useBitManip = false
val useBitManipCrypto = false
val useCryptoNIST = false
val useCryptoSM = false
override def vLen = 128 override def vLen = 128
override def vMemDataBits = 128 override def vMemDataBits = 128