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Some HarnessBinder testing with Jerry's debug suggestions.

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This commit is contained in:
James Dunn
2020-10-10 13:45:27 -07:00
parent 7d1a1539e6
commit 54acfe71fc
1 changed files with 26 additions and 26 deletions
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52
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -30,44 +30,44 @@ import scala.reflect.{ClassTag}
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[JTAGIO]) => {
ports.map { // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
case d: ClockedDMIIO => // ports.map {
// Want to error here. // case d: ClockedDMIIO =>
case j: JTAGIO => // // Want to error here.
//val dtm_success = WireInit(false.B) // case j: JTAGIO =>
//when (dtm_success) { th.success := true.B } // //val dtm_success = WireInit(false.B)
//val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) // //when (dtm_success) { th.success := true.B }
// //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success)
j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt // j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt
IOBUF(th.jd_5, j.TMS) // IOBUF(th.jd_5, j.TMS)
PULLUP(th.jd_5) // PULLUP(th.jd_5)
IOBUF(th.jd_4, j.TDI) // IOBUF(th.jd_4, j.TDI)
PULLUP(th.jd_4) // PULLUP(th.jd_4)
IOBUF(th.jd_0, j.TDO) // IOBUF(th.jd_0, j.TDO)
// mimic putting a pullup on this line (part of reset vote) // // mimic putting a pullup on this line (part of reset vote)
th.SRST_n := IOBUF(th.jd_6) // th.SRST_n := IOBUF(th.jd_6)
PULLUP(th.jd_6) // PULLUP(th.jd_6)
IOBUF(th.jd_1, j.TRSTn) // IOBUF(th.jd_1, j.TRSTn)
PULLUP(th.jd_1) // PULLUP(th.jd_1)
} // }
Nil Nil
} }
}) })
class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
//UARTAdapter.connect(ports)(system.p) // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
IOBUF(th.ck_io(2), ports.txd) // UARTAdapter.connect(ports)(system.p)
IOBUF(th.ck_io(3), ports.rxd) // IOBUF(th.ck_io(2), ports.txd)
// IOBUF(th.ck_io(3), ports.rxd)
Nil Nil
} }
}) })