Bump to latest rocket-chip

fpga/src/main/scala/arty/TestHarness.scala

@@ -25,5 +25,11 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
   def referenceClock = clock_32MHz
   def referenceReset = hReset
 
+  dut_jtag_TCK := DontCare
+  dut_jtag_TMS := DontCare
+  dut_jtag_TDI := DontCare
+  dut_jtag_TDO := DontCare
+  dut_jtag_reset := DontCare
+
   instantiateChipTops()
 }

fpga/src/main/scala/vc707/TestHarness.scala

@@ -108,6 +108,8 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
 
   _outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset)
 
+  _outer.ledModule.foreach(_ := DontCare)
+
   // reset setup
   val hReset = Wire(Reset())
   hReset := _outer.dutClock.in.head._1.reset