Support serializable endpoints; Golden Gate stage

generators/firechip/src/main/scala/EndpointBinders.scala

@@ -14,8 +14,7 @@ import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp
 import icenet.HasPeripheryIceNICModuleImpValidOnly
 
 import junctions.{NastiKey, NastiParameters}
-import midas.widgets.{IsEndpoint}
-import midas.models.{FASEDEndpoint, FasedAXI4Edge}
+import midas.models.{FASEDEndpoint, AXI4EdgeSummary, CompleteConfig}
 import firesim.endpoints._
 import firesim.configs.MemModelKey
 import firesim.util.RegisterEndpointBinder
@@ -55,11 +54,8 @@ class WithFASEDEndpoint extends RegisterEndpointBinder({
         val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
                                        axi4Bundle.ar.bits.addr.getWidth,
                                        axi4Bundle.ar.bits.id.getWidth)
-        val fasedP = p.alterPartial({
-          case NastiKey => nastiKey
-          case FasedAXI4Edge => Some(edge)
-        })
-        FASEDEndpoint(axi4Bundle, t.reset.toBool, p(MemModelKey)(fasedP))(fasedP)
+        FASEDEndpoint(axi4Bundle, t.reset.toBool,
+          CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
       })
     }).toSeq
 })

generators/firechip/src/main/scala/Generator.scala

@@ -2,7 +2,7 @@
 
 package firesim.firesim
 
-import java.io.{File}
+import java.io.{File, FileWriter}
 
 import chisel3.experimental.RawModule
 import chisel3.internal.firrtl.{Circuit, Port}
@@ -48,13 +48,14 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu
 }
 
 object FireSimGenerator extends App with IsFireSimGeneratorLike {
+  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   lazy val generatorArgs = GeneratorArgs(args)
   lazy val genDir = new File(names.targetDir)
-  elaborateAndCompileWithMidas
+  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different 
+  // JsonProtocol to properly write out the annotations. Fix once the generated are unified
+  elaborate
   generateTestSuiteMakefrags
-  generateHostVerilogHeader
   generateArtefacts
-  generateTclEnvFile
 }
 
 // For now, provide a separate generator app when not specifically building for FireSim

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -23,6 +23,8 @@ abstract class FireSimTestSuite(
   import scala.concurrent.duration._
   import ExecutionContext.Implicits.global
 
+  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+
   lazy val generatorArgs = GeneratorArgs(
     midasFlowKind = "midas",
     targetDir = "generated-src",
@@ -42,7 +44,6 @@ abstract class FireSimTestSuite(
   val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
                            s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
                            s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
-  override lazy val platform = hostParams(midas.Platform)
 
   def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
     make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"),
@@ -122,7 +123,7 @@ abstract class FireSimTestSuite(
 
   clean
   mkdirs
-  elaborateAndCompileWithMidas
+  elaborate
   generateTestSuiteMakefrags
   runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0"""))
   diffTracelog("rv64ui-p-simple.out")