Add no-reset-sync config option to disable synchronizers for simulators which don't handle async reset properly

generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala

@@ -14,13 +14,14 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.prci._
 
-import testchipip.{TLTileResetCtrl}
+import testchipip.{TLTileResetCtrl, ClockGroupFakeResetSynchronizer}
 
 case class ChipyardPRCIControlParams(
   slaveWhere: TLBusWrapperLocation = CBUS,
   baseAddress: BigInt = 0x100000,
   enableTileClockGating: Boolean = true,
-  enableTileResetSetting: Boolean = true
+  enableTileResetSetting: Boolean = true,
+  enableResetSynchronizers: Boolean = true // this should only be disable to work around verilator async-reset initialziation problems
 ) {
   def generatePRCIXBar = enableTileClockGating || enableTileResetSetting
 }
@@ -81,7 +82,9 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
   // diplomatic IOBinder should drive
   val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey))
   val clockGroupCombiner = ClockGroupCombiner()
-  val resetSynchronizer  = prci_ctrl_domain { ClockGroupResetSynchronizer() }
+  val resetSynchronizer  = prci_ctrl_domain {
+    if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer()
+  }
   val tileClockGater     = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
     val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
     clock_gater.tlNode := prci_ctrl_bus.get
@@ -94,6 +97,25 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
     reset_setter
   } }
 
+  if (!prciParams.enableResetSynchronizers) {
+    println(Console.RED + s"""
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+WARNING:
+
+DISABLING THE RESET SYNCHRONIZERS RESULTS IN
+A BROKEN DESIGN THAT WILL NOT BEHAVE
+PROPERLY AS ASIC OR FPGA.
+
+THESE SHOULD ONLY BE DISABLED TO WORK AROUND
+LIMITATIONS IN ASYNC RESET INITIALIZATION IN
+RTL SIMULATORS.
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+""" + Console.RESET)
+  }
+
   (aggregator
     := frequencySpecifier
     := clockGroupCombiner

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -95,3 +95,13 @@ class TetheredChipLikeRocketConfig extends Config(
   new chipyard.harness.WithMultiChipSerialTL(0, 1) ++                // connect the serial-tl ports of the chips together
   new chipyard.harness.WithMultiChip(0, new ChipLikeRocketConfig) ++
   new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))
+
+
+// Verilator does not initialize some of the async-reset reset-synchronizer
+// flops properly, so this config disables them.
+// This config should only be used for verilator simulations
+class VerilatorCITetheredChipLikeRocketConfig extends Config(
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++   // use absolute freqs for sims in the harness
+  new chipyard.harness.WithMultiChipSerialTL(0, 1) ++                // connect the serial-tl ports of the chips together
+  new chipyard.harness.WithMultiChip(0, new chipyard.config.WithNoResetSynchronizers ++ new ChipLikeRocketConfig) ++
+  new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))

generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala

@@ -114,3 +114,7 @@ class WithNoTileClockGaters extends Config((site, here, up) => {
 class WithNoTileResetSetters extends Config((site, here, up) => {
   case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileResetSetting = false)
 })
+
+class WithNoResetSynchronizers extends Config((site, here, up) => {
+  case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableResetSynchronizers = false)
+})