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Update AbstractConfig.scala

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-T.K.-
2024-01-01 17:50:14 -08:00
committed by GitHub
parent 40c84faa55
commit 502149d95f
1 changed files with 4 additions and 5 deletions
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generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -76,16 +76,15 @@ class AbstractConfig extends Config(
new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */
new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */
// ================================== // Debug section
// Set up tiles
// ==================================
// Debug settings
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */ new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */
// TODO: add these fragments
// new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++ // new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++
// new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ // new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */ new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */
// ==================================
// Set up tiles
// ==================================
// Cache settings // Cache settings
new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */ new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */
new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */ new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */