diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index e4e8391b..d78318f8 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -393,8 +393,8 @@ class WithClockAndResetFromHarness extends OverrideHarnessBinder({
     implicit val p = GetSystemParameters(system)
     ports.map ({
       case c: ClockWithFreq => {
-        th.setRefClockFreq(c.freqMHz)
-        c.clock := th.buildtopClock
+        val clock = th.harnessClockInstantiator.requestClockBundle(s"clock_${c.freqMHz}MHz", c.freqMHz * (1000 * 1000))
+        c.clock := clock.clock
       }
       case r: AsyncReset => r := th.buildtopReset.asAsyncReset
     })