Enabling JTAG Debuging in VCU118 FPGA

2024-02-23 16:04:28 +09:00
parent 53c6e8a996
commit 4c9bcfc123
3 changed files with 18 additions and 1 deletions
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -85,6 +85,9 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
  )))))
  ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient

+  /*** JTAG ***/
+  val jtagPlacedOverlay = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput())
+
  // module implementation
  override lazy val module = new VCU118FPGATestHarnessImp(this)
 }