Enabling JTAG Debuging in VCU118 FPGA

2024-02-23 16:04:28 +09:00
parent 53c6e8a996
commit 4c9bcfc123
3 changed files with 18 additions and 1 deletions
--- a/fpga/src/main/scala/vcu118/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala
@@ -36,3 +36,17 @@ class WithDDRMem extends HarnessBinder({
    ddrClientBundle <> port.io
  }
 })
+
+class WithJTAG extends HarnessBinder({
+  case (th: VCU118FPGATestHarnessImp, port: JTAGPort, chipId: Int) => {
+    val jtag_io = th.vcu118Outer.jtagPlacedOverlay.overlayOutput.jtag.getWrappedValue
+    port.io.TCK := jtag_io.TCK
+    port.io.TMS := jtag_io.TMS
+    port.io.TDI := jtag_io.TDI
+    jtag_io.TDO.data := port.io.TDO
+    jtag_io.TDO.driven := true.B
+    // ignore srst_n
+    jtag_io.srst_n := DontCare
+
+  }
+})