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update make variable names | change hwacha to use its own generator

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This commit is contained in:
abejgonzalez
2019-04-24 00:43:44 -07:00
parent 017a3c2350
commit 4c3dc0889c
4 changed files with 37 additions and 30 deletions
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2
common.mk
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@@ -41,7 +41,7 @@ CHISEL_ARGS ?=
$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
mkdir -p $(build_dir) mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(CHISEL_ARGS) $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"
######################################################################################### #########################################################################################
# create verilog files rules and variables # create verilog files rules and variables

4
sims/verisim/Makefile
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@@ -22,8 +22,8 @@ sim_name = verilator
# vcs simulator types and rules # vcs simulator types and rules
######################################################################################### #########################################################################################
sim_prefix = simulator sim_prefix = simulator
sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
.PHONY: default debug .PHONY: default debug
default: $(sim) default: $(sim)

4
sims/vsim/Makefile
View File

@@ -22,8 +22,8 @@ sim_name = vcs
# vcs simulator types and rules # vcs simulator types and rules
######################################################################################### #########################################################################################
sim_prefix = simv sim_prefix = simv
sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG) sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
.PHONY: default debug .PHONY: default debug
default: $(sim) default: $(sim)

57
variables.mk
View File

@@ -5,26 +5,28 @@
######################################################################################### #########################################################################################
# default variables to invoke the generator for a example Rocket system # default variables to invoke the generator for a example Rocket system
# descriptions: # descriptions:
# PROJECT = the scala package to find the MODEL/Generator in # SBT_PROJECT = the SBT project that you should find the classes/packages in
# MODEL = the top level module of the project in Chisel (normally the harness) # MODEL = the top level module of the project in Chisel (normally the harness)
# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) # VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness)
# MODEL_PACKAGE = the scala package to find the MODEL in
# CONFIG = the configuration class to give the parameters for the project # CONFIG = the configuration class to give the parameters for the project
# CFG_PROJECT = the scala package to find the CONFIG class # CONFIG_PACKAGE = the scala package to find the CONFIG class
# SBT_PROJECT = the SBT project that you should find the Generator class in # GENERATOR_PACKAGE = the scala package to find the Generator class in
# TB = wrapper over the TestHarness needed to simulate in VCS # TB = wrapper over the TestHarness needed to simulate in VCS
# TOP = top level module of the project (normally the module instantiated by the harness) # TOP = top level module of the project (normally the module instantiated by the harness)
# #
# project specific: # project specific:
# SUB_PROJECT = use the specific subproject default variables # SUB_PROJECT = use the specific subproject default variables
######################################################################################### #########################################################################################
PROJECT ?= example SBT_PROJECT ?= example
MODEL ?= RocketTestHarness MODEL ?= RocketTestHarness
VLOG_MODEL ?= TestHarness VLOG_MODEL ?= TestHarness
CONFIG ?= DefaultRocketConfig MODEL_PACKAGE ?= $(SBT_PROJECT)
CFG_PROJECT ?= $(PROJECT) CONFIG ?= DefaultRocketConfig
SBT_PROJECT ?= $(PROJECT) CONFIG_PACKAGE ?= $(SBT_PROJECT)
TB ?= TestDriver GENERATOR_PACKAGE ?= $(SBT_PROJECT)
TOP ?= RocketTop TB ?= TestDriver
TOP ?= RocketTop
######################################################################################### #########################################################################################
# subproject overrides # subproject overrides
@@ -42,28 +44,30 @@ ifeq ($(SUB_PROJECT),boomexample)
endif endif
# for BOOM developers # for BOOM developers
ifeq ($(SUB_PROJECT),boom) ifeq ($(SUB_PROJECT),boom)
PROJECT=boom.system
MODEL=TestHarness
CFG_PROJECT=boom.system
SBT_PROJECT=boom SBT_PROJECT=boom
MODEL_PACKAGE=boom.system
MODEL=TestHarness
CONFIG_PACKAGE=boom.system
GENERATOR_PACKAGE=boom.system
TOP=ExampleBoomSystem TOP=ExampleBoomSystem
endif endif
# for Rocket-chip developers # for Rocket-chip developers
ifeq ($(SUB_PROJECT),rocketchip) ifeq ($(SUB_PROJECT),rocketchip)
PROJECT=freechips.rocketchip.system
MODEL=TestHarness
CFG_PROJECT=freechips.rocketchip.system
SBT_PROJECT=rebarrocketchip SBT_PROJECT=rebarrocketchip
MODEL_PACKAGE=freechips.rocketchip.system
MODEL=TestHarness
CONFIG_PACKAGE=freechips.rocketchip.system
GENERATOR_PACKAGE=freechips.rocketchip.system
TOP=ExampleRocketSystem TOP=ExampleRocketSystem
endif endif
# for Hwacha developers # for Hwacha developers
ifeq ($(SUB_PROJECT),hwacha) ifeq ($(SUB_PROJECT),hwacha)
PROJECT=freechips.rocketchip.system
MODEL=TestHarness
CFG_PROJECT=hwacha
SBT_PROJECT=hwacha SBT_PROJECT=hwacha
MODEL_PACKAGE=freechips.rocketchip.system
MODEL=TestHarness
CONFIG_PACKAGE=hwacha
GENERATOR_PACKAGE=hwacha
TOP=ExampleRocketSystem TOP=ExampleRocketSystem
TB=TestDriver
endif endif
######################################################################################### #########################################################################################
@@ -76,11 +80,14 @@ REBAR_FIRRTL_DIR = $(base_dir)/tools/firrtl
######################################################################################### #########################################################################################
# names of various files needed to compile and run things # names of various files needed to compile and run things
######################################################################################### #########################################################################################
long_name = $(PROJECT).$(MODEL).$(CONFIG) long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG)
# if building from rocketchip, override the long_name to match what they expect # match the long_name to what the specific generator will output
ifeq ($(PROJECT),freechips.rocketchip.system) ifeq ($(GENERATOR_PACKAGE),freechips.rocketchip.system)
long_name=$(CFG_PROJECT).$(CONFIG) long_name=$(CONFIG_PACKAGE).$(CONFIG)
endif
ifeq ($(GENERATOR_PACKAGE),hwacha)
long_name=$(MODEL_PACKAGE).$(CONFIG)
endif endif
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir FIRRTL_FILE ?= $(build_dir)/$(long_name).fir