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update make variable names | change hwacha to use its own generator

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abejgonzalez
2019-04-24 00:43:44 -07:00
parent 017a3c2350
commit 4c3dc0889c
4 changed files with 37 additions and 30 deletions
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2
common.mk
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@@ -41,7 +41,7 @@ CHISEL_ARGS ?=
$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(CHISEL_ARGS) $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"
#########################################################################################
# create verilog files rules and variables