From 4c11e170b856407df2b7fb1c5f6e1c2e59887af6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 9 Feb 2021 00:47:10 -0800 Subject: [PATCH] Use series of pipe Queues instead of ShiftQueue for adding AXI4 memory delay --- .../chipyard/src/main/scala/HarnessBinders.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index 5428e342..643b2065 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -159,11 +159,11 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends OverrideHarnessBind } if (additionalLatency > 0) { withClockAndReset (port.clock, port.reset) { - mem.io.axi.aw <> ShiftQueue(Decoupled(port.bits.aw), additionalLatency) - mem.io.axi.w <> ShiftQueue(Decoupled(port.bits.w ), additionalLatency) - port.bits.b <> ShiftQueue(Decoupled(mem.io.axi.b), additionalLatency) - mem.io.axi.ar <> ShiftQueue(Decoupled(port.bits.ar), additionalLatency) - port.bits.r <> ShiftQueue(Decoupled(mem.io.axi.r), additionalLatency) + mem.io.axi.aw <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.aw))((t, _) => Queue(t, 1, pipe=true)) + mem.io.axi.w <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.w ))((t, _) => Queue(t, 1, pipe=true)) + port.bits.b <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.b))((t, _) => Queue(t, 1, pipe=true)) + mem.io.axi.ar <> (0 until additionalLatency).foldLeft(Decoupled(port.bits.ar))((t, _) => Queue(t, 1, pipe=true)) + port.bits.r <> (0 until additionalLatency).foldLeft(Decoupled(mem.io.axi.r))((t, _) => Queue(t, 1, pipe=true)) } } mem.io.clock := port.clock