diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala
index 6f6464dc..06e6aa93 100644
--- a/generators/firechip/src/main/scala/SimConfigs.scala
+++ b/generators/firechip/src/main/scala/SimConfigs.scala
@@ -3,8 +3,6 @@ package firesim.firesim
 
 import freechips.rocketchip.config.{Parameters, Config, Field}
 
-import midas.{EndpointKey}
-import midas.widgets.{EndpointMap}
 import midas.models._
 
 import firesim.endpoints._
diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala
index bf50db80..1b8b5f62 100644
--- a/generators/firechip/src/main/scala/TargetMixins.scala
+++ b/generators/firechip/src/main/scala/TargetMixins.scala
@@ -12,7 +12,6 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.TracedInstruction
 import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
 
-import midas.models.AXI4BundleWithEdge
 import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
 
 /** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */