diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala index 8e8b29fb..8a3ad2eb 100644 --- a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala @@ -3,21 +3,10 @@ package chipyard import chipyard.config.AbstractConfig import chipyard.stage.phases.TargetDirKey import freechips.rocketchip.devices.tilelink.BootROMLocated -import freechips.rocketchip.prci.AsynchronousCrossing import freechips.rocketchip.resources.BigIntHexContext import freechips.rocketchip.subsystem._ import org.chipsalliance.cde.config.Config -import radiance.memory._ -import radiance.subsystem.{RadianceGemminiDataType, WithRadianceSharedMem} - -class WithRadROMs(address: BigInt, size: Int, filename: String) extends Config((site, here, up) => { - case RadianceROMsLocated() => Some(up(RadianceROMsLocated()).getOrElse(Seq()) ++ - Seq(RadianceROMParams( - address = address, - size = size, - contentFileName = filename - ))) -}) +import radiance.subsystem.RadianceGemminiDataType class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x)) @@ -33,7 +22,13 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn // Radiance Configs // ---------------- -class RadianceBaseConfig(argsBinFilename: String = "args.bin") extends Config( +// aliases for virgo +class VirgoConfig extends RadianceClusterConfig +class VirgoFP16Config extends RadianceFP16ClusterConfig +class VirgoSynConfig extends RadianceClusterSynConfig +class VirgoFP16SynConfig extends RadianceFP16ClusterSynConfig + +class RadianceBaseConfig extends Config( // NOTE: when changing these, remember to change NUM_CORES/THREADS/WARPS in // the verilog source as well! new radiance.subsystem.WithSimtConfig(nWarps = 8, nCoreLanes = 8, nMemLanes = 8, nSrcIds = 32) ++ @@ -59,28 +54,15 @@ class RadianceFP16ClusterConfig extends Config( class RadianceClusterConfig extends Config( // important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ - new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ + // new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++ // new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++ - // - // note to hansung: somehow I don't have serializeUnaligned in my radiance subsystem files. I'll - // re-implement this with all the options instead of just this one new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ new radiance.subsystem.WithRadianceCluster(0) ++ new RadianceBaseConfig) -class RadianceClusterSmallConfig extends Config( - // important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed - new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ - new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), useVxCache = false) ++ - new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10/*KBytes*/, numBanks = 4, numWords = 8) ++ // serializeUnaligned: true - new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ - new radiance.subsystem.WithRadianceCluster(0) ++ - new RadianceBaseConfig) - class RadianceClusterSmem16KConfig extends Config( new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++ new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++ @@ -112,27 +94,6 @@ class RadianceBigLittleClusterConfig extends Config( new radiance.subsystem.WithRadianceCluster(0) ++ new RadianceBaseConfig) -class RadianceClusterConfig0 extends Config( - new radiance.subsystem.WithRadianceCores(2, location=InCluster(0), useVxCache = false) ++ - // new radiance.subsystem.WithCoalescer(nNewSrcIds = 8, enable = false) ++ - new radiance.subsystem.WithVortexL1Banks(nBanks = 4)++ - new radiance.subsystem.WithRadianceCluster(0) ++ - new RadianceBaseConfig) - -class RadianceClusterConfig1 extends Config( - new radiance.subsystem.WithRadianceCores(2, location=InCluster(0), useVxCache = false) ++ - new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++ - new radiance.subsystem.WithVortexL1Banks(nBanks = 4)++ - new radiance.subsystem.WithRadianceCluster(0) ++ - new RadianceBaseConfig("args.1.bin")) - -class RadianceClusterConfig2 extends Config( - new radiance.subsystem.WithRadianceCores(2, location=InCluster(0), useVxCache = false) ++ - new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++ - new radiance.subsystem.WithVortexL1Banks(nBanks = 4)++ - new radiance.subsystem.WithRadianceCluster(0) ++ - new RadianceBaseConfig("args.2.bin")) - class RadianceClusterSynConfig extends Config( new radiance.subsystem.WithRadianceSimParams(false) ++ new RadianceClusterConfig) @@ -145,12 +106,6 @@ class RadianceBigLittleClusterSynConfig extends Config( new radiance.subsystem.WithRadianceSimParams(false) ++ new RadianceBigLittleClusterConfig) -class RadianceGemminiConfig extends Config( - new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++ - new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++ - new RadianceBaseConfig) - class RadianceNoCacheConfig extends Config( new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++ @@ -161,24 +116,6 @@ class RadianceNoCoalConfig extends Config( new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++ new RadianceBaseConfig) -class RadianceNoCacheNoCoalConfig extends Config( - new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new RadianceBaseConfig) - -class RadianceLargeConfig extends Config( - new radiance.subsystem.WithRadianceCores(4, useVxCache = false) ++ - new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++ - new RadianceBaseConfig) - -class RadianceNoROMConfig extends Config( - new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new WithRadBootROM() ++ - new testchipip.soc.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++ - new AbstractConfig) - class RadianceFuzzerConfig extends Config( new radiance.subsystem.WithFuzzerCores(1, useVxCache = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++ @@ -187,32 +124,3 @@ class RadianceFuzzerConfig extends Config( new chipyard.harness.WithCeaseSuccess ++ new chipyard.iobinders.WithCeasePunchThrough ++ new AbstractConfig) - -class RadianceOldCacheConfig extends Config( - new radiance.subsystem.WithRadianceCores(1, useVxCache = true) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new WithRadBootROM() ++ - new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ - new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++ - new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ - new AbstractConfig -) - -// -------------------- -// Rocket-based Configs -// -------------------- - -class RocketDummyVortexConfig extends Config( - new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ - new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ - new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 16) ++ - new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ - new WithExtMemSize(BigInt("80000000", 16)) ++ - new testchipip.soc.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new AbstractConfig) - -class RocketGPUConfig extends Config( - new radiance.subsystem.WithNCustomSmallRocketCores(2) ++ - new chipyard.config.AbstractConfig) diff --git a/generators/radiance b/generators/radiance index b335132c..2929a84e 160000 --- a/generators/radiance +++ b/generators/radiance @@ -1 +1 @@ -Subproject commit b335132c342ac9fb49281fcee8b9e767380eca19 +Subproject commit 2929a84eccb160debe0803793eab2ac6cb5e3901 diff --git a/sims/vcs/pprint b/sims/vcs/pprint new file mode 100755 index 00000000..91e421d0 --- /dev/null +++ b/sims/vcs/pprint @@ -0,0 +1,142 @@ +#!/usr/bin/env python3 + +import sys +import signal +import re + +PRINT_BUF = 0x20000 / 4 + +def translator(line): + if 'core-req-wr' in line: + # Check rs1_data's last element condition + rs1_data_start = line.find('addr={') + len('addr={') + rs1_data_end = line.find('}', rs1_data_start) + rs1_data_elts = line[rs1_data_start:rs1_data_end].split(', ') + + byteen_start = line.find('byteen={') + len('byteen={') + byteen_end = line.find('}', byteen_start) + byteen_elts = line[byteen_start:byteen_end].split(', ') + + rs2_data_start = line.find('data={') + len('data={') + rs2_data_end = line.find('}', rs2_data_start) + rs2_data_elts = line[rs2_data_start:rs2_data_end].split(', ') + + # print(rs1_data_last_element) + for rs1, rs2, byteen in zip(rs1_data_elts, rs2_data_elts, byteen_elts): + if int(rs1, 16) >> 18 == 0xff0: + offset = (int(rs1, 16) - PRINT_BUF) % 65536 + if offset < 0 or offset >= 1024: + continue + else: + offset = offset % 16384 + # Extract rs2_data's last element + + hex_value = rs2[2:] # Remove the '0x' prefix + if "x" in hex_value: + continue + byteen_int = int(byteen, 16) + hex_value = "0" * (8 - len(hex_value)) + hex_value + bytes_object = bytes.fromhex(hex_value) # .replace(b"\x00", b"") + + masked_bytes_list = [] + + assert(len(bytes_object) == 4) + + for i, byte in enumerate(bytes_object[::-1]): + if byteen_int & (1 << i): + masked_bytes_list.append(byte) + + reversed_bytes = bytes(masked_bytes_list) + # print(reversed_bytes.decode('utf-8', errors="ignore")) + try: + return reversed_bytes.decode('ascii', errors="ignore") + except UnicodeDecodeError: + return "" + +def timestamp_parser(line): + parts = line.strip().split() + if parts: + return parts[0][:-1] + else: + return "" + +sim_started = False +sim_ended = False + +def signal_handler(sig, frame): + if sim_started: + print("\033[u") + sys.exit(0) + +def main(): + signal.signal(signal.SIGINT, signal_handler) + + current_timestamp = "" + re_start_num = re.compile(r"^\s*[0-9]+:") + + print("\033[2J\033[H") + + ts_countdown = 100 + global sim_started, sim_ended + perf_counters = False + hang_detector = 0 + + for line in sys.stdin: + line = line.rstrip('\n') + ts_countdown -= 1 + + if "Chronologic VCS simulator" in line: + sim_started = True + + sim_nontrace = re.match(re_start_num, line) is None + + if "has no more active warps" in line: + sim_ended = True + + if "====================CORE" in line: + perf_counters = True + if hang_detector >= 8: + print("\n\033[3mpossible hang detected\033[0m\n") + + if (not sim_started) or sim_ended: + if "has no more active warps" not in line: + print(line) + continue + elif sim_started and (not sim_ended): + if sim_nontrace: + if not perf_counters: + print(line) + elif line.startswith("dcache stores:"): + perf_counters = False + hang_detector += 1 + continue + else: + hang_detector = 0 + + if ts_countdown == 0: + timestamp = timestamp_parser(line) + + if timestamp: + current_timestamp = timestamp + # Save cursor position + print("\033[s", end='') + # Move cursor to top-left corner, clear line, bold, timestamp, unbold + print("\033[H\033[2K\033[1", current_timestamp, "\033[0m", end='') + # Restore cursor position + print("\033[u", end='') + ts_countdown = 100 + else: + ts_countdown = 1 + + ts_countdown -= 1 + translated_line = translator(line) + + if translated_line: + print(translated_line, end='') + sys.stdout.flush() + + print("") + +if __name__ == '__main__': + main() +