diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index e36805ec..84bfc5fb 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -130,38 +130,7 @@ Using the JTAG Interface ------------------------ The main way to use JTAG with a Rocket Chip based system is to instantiate the Debug Transfer Module (DTM) -and configure it to use a JTAG interface (by default the DTM is setup to use the DMI interface mentioned above). - -Creating a DTM+JTAG Config -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -First, a DTM config must be created for the system that you want to create. -This step is similar to the DMI simulation section within the :ref:`Starting the TSI or DMI Simulation` section. -The configuration is very similar to a DMI-based configuration. The main difference -is the addition of the ``WithJtagDTM`` config fragment that configures the instantiated DTM to use the JTAG protocol as the -bringup method. - -.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala - :language: scala - :start-after: DOC include start: JtagRocket - :end-before: DOC include end: JtagRocket - -Building a DTM+JTAG Simulator -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -After creating the config, call the ``make`` command like the following to build a simulator for your RTL: - -.. code-block:: bash - - cd sims/verilator - # or - cd sims/vcs - - make CONFIG=jtagRocketConfig - -In this example, the simulation will use the config that you previously specified, as well as set -the other parameters that are needed to satisfy the build system. After that point, you -should have a JTAG enabled simulator that you can attach to using OpenOCD and GDB! +and configure it to use a JTAG interface. The default Chipyard designs configure the DTM to use JTAG. you may attach OpenOCD and GDB to any of the default JTAG-enabled designs. Debugging with JTAG ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 6336c05a..cfa465e7 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.config.{Field, Parameters, Config} import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.{BootROMLocated} -import freechips.rocketchip.devices.debug.{Debug} +import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} import freechips.rocketchip.groundtest.{GroundTestSubsystem} import freechips.rocketchip.tile._ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} @@ -163,3 +163,10 @@ class WithTileDividedClock extends Config((site, here, up) => { case ClockingSchemeKey => ClockingSchemeGenerators.harnessDividedClock }) +class WithDMIDTM extends Config((site, here, up) => { + case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) +}) + +class WithNoDebug extends Config((site, here, up) => { + case DebugModuleKey => None +}) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index f13a6882..54a0d1dc 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -167,6 +167,7 @@ object AddIOCells { /** * Add IO cells to a debug module and name the IO ports, for debug IO which must go off-chip * For on-chip debug IO, drive them appropriately + * Mostly copied from rocket-chip/src/main/scala/devices/debug/Periphery.scala * @param system A BaseSubsystem that might have a debug module * @return Returns a tuple2 of (Generated debug io ports, Generated IOCells) */ @@ -175,27 +176,22 @@ object AddIOCells { val tlbus = system.outer.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere) val debug_clock = Wire(Clock()).suggestName("debug_clock") val debug_reset = Wire(Reset()).suggestName("debug_reset") - debug_clock := false.B.asClock - debug_reset := false.B + debug_clock := false.B.asClock // must provide default assignment to avoid firrtl unassigned error + debug_reset := false.B // must provide default assignment to avoid firrtl unassigned error BoringUtils.bore(tlbus.module.clock, Seq(debug_clock)) BoringUtils.bore(tlbus.module.reset, Seq(debug_reset)) // We never use the PSDIO, so tie it off on-chip system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) } - - // Set resetCtrlOpt with the system reset system.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := debug_reset.asBool } } - system.debug.map { d => // Tie off extTrigger d.extTrigger.foreach { t => t.in.req := false.B t.out.ack := t.out.req } - // Tie off disableDebug d.disableDebug.foreach { d => d := false.B } - // Drive JTAG on-chip IOs d.systemjtag.map { j => j.reset := debug_reset @@ -204,15 +200,9 @@ object AddIOCells { j.version := system.p(JtagDTMKey).idcodeVersion.U(4.W) } } - - - // Connect DebugClockAndReset to system implicit clock. TODO this should use the clock of the bus the debug module is attached to - - Debug.connectDebugClockAndReset(Some(debug), debug_clock)(system.p) // Add IOCells for the DMI/JTAG/APB ports - val dmiTuple = debug.clockeddmi.map { d => IOCell.generateIOFromSignal(d, Some("iocell_dmi"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) } @@ -412,7 +402,7 @@ class WithSimDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { val (ports, iocells) = AddIOCells.debug(system)(system.p) val harnessFn = (th: HasHarnessSignalReferences) => { - val dtm_success = Wire(Bool()) + val dtm_success = WireInit(false.B) when (dtm_success) { th.success := true.B } ports.map { case d: ClockedDMIIO => @@ -437,8 +427,8 @@ class WithTiedOffDebug extends OverrideIOBinder({ d.dmi.req.valid := false.B d.dmi.req.bits := DontCare d.dmi.resp.ready := true.B - d.dmiClock := th.harnessClock - d.dmiReset := th.harnessReset + d.dmiClock := false.B.asClock + d.dmiReset := true.B case j: JTAGIO => j.TCK := true.B.asClock j.TMS := true.B diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 2b9473ed..a925ec56 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -11,13 +11,14 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a blackbox DRAMSim model - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimDebug ++ // attach SimJTAG new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks + new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index 7bc985aa..6bc7cf69 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -14,6 +14,6 @@ class ArianeConfig extends Config( class dmiArianeConfig extends Config( new chipyard.iobinders.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial - new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation, override default tie-off debug + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new ariane.WithNArianeCores(1) ++ // single Ariane core new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 07033609..420ba192 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -23,18 +23,10 @@ class GemminiRocketConfig extends Config( new chipyard.config.AbstractConfig) // DOC include end: GemminiRocketConfig -// DOC include start: JtagRocket -class jtagRocketConfig extends Config( - new chipyard.iobinders.WithSimDebug ++ // add SimDebug, in addition to default SimSerial - new freechips.rocketchip.subsystem.WithJtagDTM ++ // sets DTM communication interface to JTAG - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new chipyard.config.AbstractConfig) -// DOC include end: JtagRocket - // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new chipyard.iobinders.WithTiedOffSerial ++ // tie-off serial, override default add SimSerial - new chipyard.iobinders.WithSimDebug ++ // add SimDebug, override default tie-off debug + new chipyard.iobinders.WithTiedOffSerial ++ // don't use serial to drive the chip, since we use DMI instead + new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) // DOC include end: DmiRocket diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index 8872ed5e..d501b6c0 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -23,7 +23,7 @@ class TutorialStarterConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // Connect a SimUART adapter to display UART on stdout new chipyard.iobinders.WithBlackBoxSimMem ++ // Connect simulated external memory new chipyard.iobinders.WithTieOffInterrupts ++ // Do not simulate external interrupts - new chipyard.iobinders.WithTiedOffDebug ++ // Disconnect the debug module, since we use TSI for bring-up + new chipyard.iobinders.WithSimDebug ++ // Connect SimJTAG (or SimDTM) widgets to debug ios new chipyard.iobinders.WithSimSerial ++ // Connect external SimSerial widget to drive TSI // Config fragments below this line affect hardware generation @@ -43,13 +43,19 @@ class TutorialStarterConfig extends Config( // Uncomment this line, and specify a size if you want to have a L2 // new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks=1, nWays=4, capacityKB=128) ++ + // Set the debug module to expose an external JTAG port + new freechips.rocketchip.subsystem.WithJtagDTM ++ + // For simpler designs, we want to minimize IOs on // our Top. These config fragments remove unnecessary // ports new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + + // Use the standard hierarchical bus topology including mbus+l2 + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + // BaseConfig configures "bare" rocketchip system new freechips.rocketchip.system.BaseConfig ) @@ -60,7 +66,7 @@ class TutorialMMIOConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -76,6 +82,7 @@ class TutorialMMIOConfig extends Config( // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ @@ -88,7 +95,7 @@ class TutorialSha3Config extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -101,6 +108,7 @@ class TutorialSha3Config extends Config( // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ @@ -114,7 +122,7 @@ class TutorialSha3BlackBoxConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -128,6 +136,7 @@ class TutorialSha3BlackBoxConfig extends Config( // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++