[docs][ci skip] Address comments
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@@ -7,13 +7,16 @@ IP, or by modifying existing Chisel generators. Such changes might introduce
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bugs. This section aims to run through a typical debugging flow
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bugs. This section aims to run through a typical debugging flow
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using Chipyard. We assume the user has a custom SoC configuration,
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using Chipyard. We assume the user has a custom SoC configuration,
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and is trying to verify functionality by running some software test.
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and is trying to verify functionality by running some software test.
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We also assume the software has already been verified on a functional
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simulator, such as Spike or QEMU. This section will focus on debugging
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hardware.
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Waveforms
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Waveforms
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---------------------------
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---------------------------
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The default SW simulators do not dump waveforms during execution. To build
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The default software RTL simulators do not dump waveforms during execution.
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simulators with wave dump capabilities use must use the ``debug`` make target.
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To build simulators with wave dump capabilities use must use the ``debug``
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For example:
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make target. For example:
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.. code-block:: shell
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.. code-block:: shell
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@@ -81,5 +84,6 @@ directory.
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Firesim Debugging
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Firesim Debugging
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---------------------------
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---------------------------
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Chisel printfs, asserts, and waveform generation are also available in FireSim
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Chisel printfs, asserts, and waveform generation are also available in FireSim
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FPGA-accelerated simulation. See the FireSim docs for more detail.
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FPGA-accelerated simulation. See the FireSim
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`documentation <https://docs.fires.im/en/latest/>`__ for more detail.
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@@ -10,4 +10,5 @@ They expect you to know about Chisel, Parameters, Configs, etc.
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Top-Testharness
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Top-Testharness
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Chip-Communication
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Chip-Communication
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Debugging-RTL
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Resources
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Resources
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@@ -18,6 +18,5 @@ Hit next to get started!
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Chipyard-Components
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Chipyard-Components
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Configs-Parameters-Mixins
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Configs-Parameters-Mixins
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Initial-Repo-Setup
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Initial-Repo-Setup
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Debugging-RTL
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