update chip communication with pictures | update spike [ci skip]

docs/Software/Spike.rst

@@ -2,7 +2,7 @@ The RISC-V ISA Simulator (Spike)
 =================================
 
 Spike is the golden reference functional RISC-V ISA C++ sofware simulator.
-It provides full system emulation or proxied emulation with the HTIF/FESVR.
+It provides full system emulation or proxied emulation with `HTIF/FESVR <https://github.com/riscv/riscv-isa-sim/tree/master/fesvr>`__.
 It serves as a starting point for running software on a RISC-V target.
 Here is a highlight of some of Spikes main features:
 
@@ -15,5 +15,9 @@ Here is a highlight of some of Spikes main features:
 * JTAG support
 * Highly extensible (add and test new instructions)
 
+In most cases, software development for a Chipyard target will begin with functional simulation using Spike
+(usually with the addition of custom Spike models for custom accelerator functions), and only later move on to
+full cycle-accurate simulation using software RTL simulators or FireSim.
+
 Spike comes pre-packaged in the RISC-V toolchain and is available on the path as ``spike``.
 More information can be found in the `Spike repository <https://github.com/riscv/riscv-isa-sim>`__.