From 8b3fef85cefdb98938e85e5cc01d7f529ba51b15 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 17:44:47 -0700 Subject: [PATCH 01/13] first attempt at heter. port --- .../main/scala/BoomAndRocketSubsystem.scala | 94 ++++++++++++++ .../example/src/main/scala/ConfigMixins.scala | 66 ++++++++++ .../example/src/main/scala/Configs.scala | 120 +++++++++++++++++- .../scala/ExampleBoomAndRocketSystem.scala | 62 +++++++++ .../example/src/main/scala/TestHarness.scala | 35 +++++ generators/example/src/main/scala/Top.scala | 57 +++++++++ variables.mk | 12 ++ 7 files changed, 444 insertions(+), 2 deletions(-) create mode 100644 generators/example/src/main/scala/BoomAndRocketSubsystem.scala create mode 100644 generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala diff --git a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala new file mode 100644 index 00000000..275414ff --- /dev/null +++ b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala @@ -0,0 +1,94 @@ +package example + +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ + +import boom.system.{BoomTilesKey} + +trait HasBoomAndRocketTiles extends HasTiles + with CanHavePeripheryPLIC + with CanHavePeripheryCLINT + with HasPeripheryDebug +{ this: BaseSubsystem => + + val module: HasBoomAndRocketTilesModuleImp + + protected val rocketTileParams = p(RocketTilesKey) + protected val boomTileParams = p(BoomTilesKey) + private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) + private val boomCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), boomTileParams.size) + + // Make a tile and wire its nodes into the system, + // according to the specified type of clock crossing. + // Note that we also inject new nodes into the tile itself, + // also based on the crossing type. + val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) => + val rocket = LazyModule(new RocketTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) + + connectMasterPortsToSBus(rocket, crossing) + connectSlavePortsToCBus(rocket, crossing) + connectInterrupts(rocket, Some(debug), clintOpt, plicOpt) + + rocket + } + + println(s"DEBUG: Amount of rocket tiles: ${rocketTiles.length}") + + val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) => + val boomCore = LazyModule( + new boom.common.BoomTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) + + connectMasterPortsToSBus(boomCore, crossing) + connectSlavePortsToCBus(boomCore, crossing) + connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt) + + boomCore + } + + println(s"DEBUG: Amount of boom tiles: ${boomTiles.length}") + + val boomAndRocketTiles = rocketTiles ++ boomTiles + println(s"DEBUG: Amount of both tiles: ${boomAndRocketTiles.length}") + + def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++ + (boomTiles map { t => t.module.core.coreMonitorBundle}).toList + + def getOMRocketInterruptTargets(): Seq[OMInterruptTarget] = + boomAndRocketTiles.flatMap(c => c.cpuDevice.getInterruptTargets()) + + def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] = + boomAndRocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap)) +} + +trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp + with HasPeripheryDebugModuleImp { + val outer: HasBoomAndRocketTiles +} + +class BoomAndRocketSubsystem(implicit p: Parameters) extends BaseSubsystem + with HasBoomAndRocketTiles { + val tiles = boomAndRocketTiles + override lazy val module = new BoomAndRocketSubsystemModuleImp(this) +} + +class BoomAndRocketSubsystemModuleImp[+L <: BoomAndRocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) + with HasBoomAndRocketTilesModuleImp { + tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => + wire.clock := clock + wire.reset := reset + wire.hartid := i.U + wire.reset_vector := global_reset_vector + } +} diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 5551a66d..02e4ea22 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -168,3 +168,69 @@ class WithGPIOBoomTop extends Config((site, here, up) => { top } }) + +// -------------------------------------- +// BOOM + Rocket Top Level System Parameter Mixins +// -------------------------------------- + +/** + * Class to specify a "plain" top level BOOM + Rocket system + */ +class WithNormalBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomAndRocketTop()(p)).module) + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with PWM + */ +class WithPWMBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomAndRocketTopWithPWMTL()(p)).module) +}) + +/** + * Class to specify a top level BOOM + Rocket system with a PWM AXI4 + */ +class WithPWMAXI4BoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomAndRocketTopWithPWMAXI4()(p)).module) +}) + +/** + * Class to specify a top level BOOM + Rocket system with a block device + */ +class WithBlockDeviceModelBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) + top.connectBlockDeviceModel() + top + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with a simulator block device + */ +class WithSimBlockDeviceBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) + top.connectSimBlockDevice(clock, reset) + top + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with GPIO + */ +class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithGPIO()(p)).module) + for (gpio <- top.gpio) { + for (pin <- gpio.pins) { + pin.i.ival := false.B + } + } + top + } +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 68ca289c..97f08d62 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -106,10 +106,28 @@ class BlockDeviceModelBoomConfig extends Config( new WithBlockDeviceModelBoomTop ++ new BaseBoomConfig) +/** + * Slightly different looking configs since we need to override + * the `WithNBoomCores` with the DefaultBoomConfig params + */ class DualCoreBoomConfig extends Config( - // Core gets tacked onto existing list + new WithNormalBoomTop ++ + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(2) ++ - new DefaultBoomConfig) + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.system.BaseConfig) + +class DualCoreSmallBoomConfig extends Config( + new WithNormalBoomTop ++ + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.WithSmallBooms ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.system.BaseConfig) class RV32BoomConfig extends Config( new WithBootROM ++ @@ -119,3 +137,101 @@ class GPIOBoomConfig extends Config( new WithGPIO ++ new WithGPIOBoomTop ++ new BaseBoomConfig) + +// --------------------- +// BOOM + Rocket Configs +// --------------------- + +//class BaseRocketConfig extends Config( +// new WithBootROM ++ +// new freechips.rocketchip.system.DefaultConfig) +// +//class DefaultRocketConfig extends Config( +// new WithNormalRocketTop ++ +// new BaseRocketConfig) +// +//class BaseConfig extends Config( +// new WithDefaultMemPort() ++ +// new WithDefaultMMIOPort() ++ +// new WithDefaultSlavePort() ++ +// new WithTimebase(BigInt(1000000)) ++ // 1 MHz +// new WithDTS("freechips,rocketchip-unknown", Nil) ++ +// new WithNExtTopInterrupts(2) ++ +// new BaseSubsystemConfig() +//) +// +//class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig) +// +////boom +// new WithRVC ++ +// new DefaultBoomConfig ++ +// new WithNBoomCores(1) ++ +// new WithoutTLMonitors ++ +// new freechips.rocketchip.system.BaseConfig) + +class BaseBoomAndRocketConfig extends Config( + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +//class BaseBoomAndRocketConfig extends Config( +// new WithBootROM ++ +// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ +// new boom.system.BoomConfig) + +class SmallBaseBoomAndRocketConfig extends Config( + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new boom.system.SmallBoomConfig) + +class DefaultBoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class SmallDefaultBoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new SmallBaseBoomAndRocketConfig) + +class HwachaBoomAndRocketConfig extends Config( + new hwacha.DefaultHwachaConfig ++ + new DefaultBoomAndRocketConfig) + +class RoccBoomAndRocketConfig extends Config( + new WithRoccExample ++ + new DefaultBoomAndRocketConfig) + +class PWMBoomAndRocketConfig extends Config( + new WithPWMBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class PWMAXI4BoomAndRocketConfig extends Config( + new WithPWMAXI4BoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class SimBlockDeviceBoomAndRocketConfig extends Config( + new WithBlockDevice ++ + new WithSimBlockDeviceBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class BlockDeviceModelBoomAndRocketConfig extends Config( + new WithBlockDevice ++ + new WithBlockDeviceModelBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class DualCoreBoomAndOneRocketConfig extends Config( + // Core gets tacked onto existing list + new boom.system.WithNBoomCores(2) ++ + new DefaultBoomAndRocketConfig) + +class RV32BoomAndNormalRocketConfig extends Config( + new WithBootROM ++ + new boom.system.SmallRV32UnifiedBoomConfig) + +class GPIOBoomAndRocketConfig extends Config( + new WithGPIO ++ + new WithGPIOBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) diff --git a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala new file mode 100644 index 00000000..cc7fd3db --- /dev/null +++ b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala @@ -0,0 +1,62 @@ +package example + +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ + +import boom.system.{BoomTilesKey} + +/** + * Example top with periphery devices and ports, and a BOOM subsystem + */ +class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem + with HasAsyncExtInterrupts + with boom.system.CanHaveMisalignedMasterAXI4MemPort + with CanHaveMasterAXI4MMIOPort + with CanHaveSlaveAXI4Port + with HasPeripheryBootROM +{ + override lazy val module = new ExampleBoomAndRocketSystemModule(this) + + // The sbus masters the cbus; here we convert TL-UH -> TL-UL + sbus.crossToBus(cbus, NoCrossing) + + // The cbus masters the pbus; which might be clocked slower + cbus.crossToBus(pbus, SynchronousCrossing()) + + // The fbus masters the sbus; both are TL-UH or TL-C + FlipRendering { implicit p => + sbus.crossFromBus(fbus, SynchronousCrossing()) + } + + // The sbus masters the mbus; here we convert TL-C -> TL-UH + private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) + private val (in, out, halt) = coherenceManager(this) + if (nBanks != 0) { + sbus.coupleTo("coherence_manager") { in :*= _ } + mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } + } +} + +/** + * Example top module with periphery devices and ports, and a BOOM subsystem + */ +class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer) + with HasRTCModuleImp + with HasExtInterruptsModuleImp + with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MMIOPortModuleImp + with CanHaveSlaveAXI4PortModuleImp + with HasPeripheryBootROMModuleImp + with DontTouch diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index b7120329..a517b6b8 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -77,3 +77,38 @@ class BoomTestHarness(implicit val p: Parameters) extends Module { }) io.success := dut.connectSimSerial() } + +// -------------------------- +// BOOM + Rocket Test Harness +// -------------------------- + +case object BuildBoomAndRocketTop extends Field[(Clock, Bool, Parameters) => BoomAndRocketTopModule[BoomAndRocketTop]] + +class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + // force Chisel to rename module + override def desiredName = "TestHarness" + + val dut = p(BuildBoomAndRocketTop)(clock, reset.toBool, p) + dut.debug := DontCare + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + io.success := dut.connectSimSerial() +} diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 8a39e3d1..50e5d0c6 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -127,3 +127,60 @@ class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop class BoomTopWithGPIOModule(l: BoomTopWithGPIO) extends BoomTopModule(l) with HasPeripheryGPIOModuleImp + +// ------------------------------- +// BOOM + Rocket Top Level Systems +// ------------------------------- + +class BoomAndRocketTop(implicit p: Parameters) extends ExampleBoomAndRocketSystem + with HasNoDebug + with HasPeripherySerial { + override lazy val module = new BoomAndRocketTopModule(this) +} + +class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends ExampleBoomAndRocketSystemModule(l) + with HasRTCModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with DontTouch + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithPWMTL(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryPWMTL { + override lazy val module = new BoomAndRocketTopWithPWMTLModule(this) +} + +class BoomAndRocketTopWithPWMTLModule(l: BoomAndRocketTopWithPWMTL) extends BoomAndRocketTopModule(l) + with HasPeripheryPWMTLModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryPWMAXI4 { + override lazy val module = new BoomAndRocketTopWithPWMAXI4Module(this) +} + +class BoomAndRocketTopWithPWMAXI4Module(l: BoomAndRocketTopWithPWMAXI4) extends BoomAndRocketTopModule(l) + with HasPeripheryPWMAXI4ModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithBlockDevice(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryBlockDevice { + override lazy val module = new BoomAndRocketTopWithBlockDeviceModule(this) +} + +class BoomAndRocketTopWithBlockDeviceModule(l: BoomAndRocketTopWithBlockDevice) extends BoomAndRocketTopModule(l) + with HasPeripheryBlockDeviceModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithGPIO(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryGPIO { + override lazy val module = new BoomAndRocketTopWithGPIOModule(this) +} + +class BoomAndRocketTopWithGPIOModule(l: BoomAndRocketTopWithGPIO) + extends BoomAndRocketTopModule(l) + with HasPeripheryGPIOModuleImp diff --git a/variables.mk b/variables.mk index 0808003c..62cd35ce 100644 --- a/variables.mk +++ b/variables.mk @@ -50,6 +50,18 @@ ifeq ($(SUB_PROJECT),boomexample) TB ?= TestDriver TOP ?= BoomTop endif +# for a BOOM + Rocket based example system +ifeq ($(SUB_PROJECT),boomrocketexample) + SBT_PROJECT ?= example + MODEL ?= BoomAndRocketTestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= $(SBT_PROJECT) + CONFIG ?= DefaultBoomAndRocketConfig + CONFIG_PACKAGE ?= $(SBT_PROJECT) + GENERATOR_PACKAGE ?= $(SBT_PROJECT) + TB ?= TestDriver + TOP ?= BoomAndRocketTop +endif # for BOOM developers ifeq ($(SUB_PROJECT),boom) SBT_PROJECT ?= boom From cae63ad13fffce885fe704e8f26861920be392cd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 23:29:48 -0700 Subject: [PATCH 02/13] working heterogenous cores --- .../example/src/main/scala/ConfigMixins.scala | 26 ++++- .../example/src/main/scala/Configs.scala | 99 +++++++++---------- 2 files changed, 70 insertions(+), 55 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 02e4ea22..2816352d 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -1,14 +1,20 @@ package example import chisel3._ +import chisel3.util.{log2Up} + import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.{XLen} +import freechips.rocketchip.tile.{XLen, MaxHartIdBits} + import testchipip._ + import sifive.blocks.devices.gpio._ +import boom.system.{BoomTilesKey} + /** * TODO: Why do we need this? */ @@ -234,3 +240,19 @@ class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { top } }) + +/** + * Class to renumber BOOM + Rocket harts so that there are no overlapped harts + * This mixin assumes Rocket tiles are numbered before BOOM tiles + * Also makes support for multiple harts depend on Rocket + BOOM + * Note: Must come after all harts are assigned for it to apply + */ +class WithRenumberHarts extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => + r.copy(hartId = i) + } + case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => + b.copy(hartId = i + up(RocketTilesKey, site).length) + } + case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 97f08d62..74e9a131 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -1,8 +1,10 @@ package example import chisel3._ + import freechips.rocketchip.config.{Config} import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks} + import testchipip._ // -------------- @@ -43,6 +45,11 @@ class BlockDeviceModelRocketConfig extends Config( new WithBlockDeviceModelRocketTop ++ new BaseRocketConfig) +class GPIORocketConfig extends Config( + new WithGPIO ++ + new WithGPIORocketTop ++ + new BaseRocketConfig) + class DualCoreRocketConfig extends Config( new WithNBigCores(2) ++ new DefaultRocketConfig) @@ -51,11 +58,6 @@ class RV32RocketConfig extends Config( new WithRV32 ++ new DefaultRocketConfig) -class GPIORocketConfig extends Config( - new WithGPIO ++ - new WithGPIORocketTop ++ - new BaseRocketConfig) - class GB1MemoryConfig extends Config( new WithExtMemSize((1<<30) * 1L) ++ new DefaultRocketConfig) @@ -106,6 +108,11 @@ class BlockDeviceModelBoomConfig extends Config( new WithBlockDeviceModelBoomTop ++ new BaseBoomConfig) +class GPIOBoomConfig extends Config( + new WithGPIO ++ + new WithGPIOBoomTop ++ + new BaseBoomConfig) + /** * Slightly different looking configs since we need to override * the `WithNBoomCores` with the DefaultBoomConfig params @@ -129,48 +136,18 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) -class RV32BoomConfig extends Config( +class RV32UnifiedBoomConfig extends Config( + new WithNormalBoomTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) -class GPIOBoomConfig extends Config( - new WithGPIO ++ - new WithGPIOBoomTop ++ - new BaseBoomConfig) - // --------------------- // BOOM + Rocket Configs // --------------------- -//class BaseRocketConfig extends Config( -// new WithBootROM ++ -// new freechips.rocketchip.system.DefaultConfig) -// -//class DefaultRocketConfig extends Config( -// new WithNormalRocketTop ++ -// new BaseRocketConfig) -// -//class BaseConfig extends Config( -// new WithDefaultMemPort() ++ -// new WithDefaultMMIOPort() ++ -// new WithDefaultSlavePort() ++ -// new WithTimebase(BigInt(1000000)) ++ // 1 MHz -// new WithDTS("freechips,rocketchip-unknown", Nil) ++ -// new WithNExtTopInterrupts(2) ++ -// new BaseSubsystemConfig() -//) -// -//class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig) -// -////boom -// new WithRVC ++ -// new DefaultBoomConfig ++ -// new WithNBoomCores(1) ++ -// new WithoutTLMonitors ++ -// new freechips.rocketchip.system.BaseConfig) - class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ + new WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(1) ++ @@ -178,15 +155,16 @@ class BaseBoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) -//class BaseBoomAndRocketConfig extends Config( -// new WithBootROM ++ -// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ -// new boom.system.BoomConfig) - class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ + new WithRenumberHarts ++ + new boom.common.WithRVC ++ + new boom.common.WithSmallBooms ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new boom.system.SmallBoomConfig) + new freechips.rocketchip.system.BaseConfig) class DefaultBoomAndRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ @@ -222,16 +200,31 @@ class BlockDeviceModelBoomAndRocketConfig extends Config( new WithBlockDeviceModelBoomAndRocketTop ++ new BaseBoomAndRocketConfig) -class DualCoreBoomAndOneRocketConfig extends Config( - // Core gets tacked onto existing list - new boom.system.WithNBoomCores(2) ++ - new DefaultBoomAndRocketConfig) - -class RV32BoomAndNormalRocketConfig extends Config( - new WithBootROM ++ - new boom.system.SmallRV32UnifiedBoomConfig) - class GPIOBoomAndRocketConfig extends Config( new WithGPIO ++ new WithGPIOBoomAndRocketTop ++ new BaseBoomAndRocketConfig) + +class DualCoreBoomAndOneRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new WithBootROM ++ + new WithRenumberHarts ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class RV32BoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new WithBootROM ++ + new WithRenumberHarts ++ + new boom.common.WithBoomRV32 ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new WithRV32 ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) From e538e333a5be1af1903d89932554234b61302c88 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 21 May 2019 10:47:24 -0700 Subject: [PATCH 03/13] updated boom for fixes \ better printf From 838a34be51e57832b72d13b9b35172f068236437 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 19:26:08 -0700 Subject: [PATCH 04/13] move subsystem to boom | misc cleanup | bump boom --- generators/boom | 2 +- .../main/scala/BoomAndRocketSubsystem.scala | 94 ------------------- .../example/src/main/scala/ConfigMixins.scala | 82 ---------------- .../example/src/main/scala/Configs.scala | 28 +++--- .../scala/ExampleBoomAndRocketSystem.scala | 62 ------------ .../example/src/main/scala/TestHarness.scala | 35 ------- generators/example/src/main/scala/Top.scala | 61 +----------- variables.mk | 5 +- 8 files changed, 19 insertions(+), 350 deletions(-) delete mode 100644 generators/example/src/main/scala/BoomAndRocketSubsystem.scala delete mode 100644 generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala diff --git a/generators/boom b/generators/boom index 8d3162cb..ff8c25af 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 8d3162cbbe6f0db19a39a2f22226ab9eb6edea31 +Subproject commit ff8c25af0b14c7eba67451f574e1ddacaaf8a5b6 diff --git a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala deleted file mode 100644 index 275414ff..00000000 --- a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala +++ /dev/null @@ -1,94 +0,0 @@ -package example - -import chisel3._ -import chisel3.internal.sourceinfo.{SourceInfo} - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ - -import boom.system.{BoomTilesKey} - -trait HasBoomAndRocketTiles extends HasTiles - with CanHavePeripheryPLIC - with CanHavePeripheryCLINT - with HasPeripheryDebug -{ this: BaseSubsystem => - - val module: HasBoomAndRocketTilesModuleImp - - protected val rocketTileParams = p(RocketTilesKey) - protected val boomTileParams = p(BoomTilesKey) - private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) - private val boomCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), boomTileParams.size) - - // Make a tile and wire its nodes into the system, - // according to the specified type of clock crossing. - // Note that we also inject new nodes into the tile itself, - // also based on the crossing type. - val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) => - val rocket = LazyModule(new RocketTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) - - connectMasterPortsToSBus(rocket, crossing) - connectSlavePortsToCBus(rocket, crossing) - connectInterrupts(rocket, Some(debug), clintOpt, plicOpt) - - rocket - } - - println(s"DEBUG: Amount of rocket tiles: ${rocketTiles.length}") - - val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) => - val boomCore = LazyModule( - new boom.common.BoomTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) - - connectMasterPortsToSBus(boomCore, crossing) - connectSlavePortsToCBus(boomCore, crossing) - connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt) - - boomCore - } - - println(s"DEBUG: Amount of boom tiles: ${boomTiles.length}") - - val boomAndRocketTiles = rocketTiles ++ boomTiles - println(s"DEBUG: Amount of both tiles: ${boomAndRocketTiles.length}") - - def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++ - (boomTiles map { t => t.module.core.coreMonitorBundle}).toList - - def getOMRocketInterruptTargets(): Seq[OMInterruptTarget] = - boomAndRocketTiles.flatMap(c => c.cpuDevice.getInterruptTargets()) - - def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] = - boomAndRocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap)) -} - -trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp - with HasPeripheryDebugModuleImp { - val outer: HasBoomAndRocketTiles -} - -class BoomAndRocketSubsystem(implicit p: Parameters) extends BaseSubsystem - with HasBoomAndRocketTiles { - val tiles = boomAndRocketTiles - override lazy val module = new BoomAndRocketSubsystemModuleImp(this) -} - -class BoomAndRocketSubsystemModuleImp[+L <: BoomAndRocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) - with HasBoomAndRocketTilesModuleImp { - tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => - wire.clock := clock - wire.reset := reset - wire.hartid := i.U - wire.reset_vector := global_reset_vector - } -} diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 2816352d..363f0895 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -109,72 +109,6 @@ class WithGPIORocketTop extends Config((site, here, up) => { } }) -// -------------------------------------- -// BOOM Top Level System Parameter Mixins -// -------------------------------------- - -/** - * Class to specify a "plain" top level BOOM system - */ -class WithNormalBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomTop()(p)).module) - } -}) - -/** - * Class to specify a top level BOOM system with PWM - */ -class WithPWMBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMTL()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a PWM AXI4 - */ -class WithPWMAXI4BoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a block device - */ -class WithBlockDeviceModelBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -/** - * Class to specify a top level BOOM system with a simulator block device - */ -class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -/** - * Class to specify a top level BOOM system with GPIO - */ -class WithGPIOBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module) - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } -}) - // -------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins // -------------------------------------- @@ -240,19 +174,3 @@ class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { top } }) - -/** - * Class to renumber BOOM + Rocket harts so that there are no overlapped harts - * This mixin assumes Rocket tiles are numbered before BOOM tiles - * Also makes support for multiple harts depend on Rocket + BOOM - * Note: Must come after all harts are assigned for it to apply - */ -class WithRenumberHarts extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => - r.copy(hartId = i) - } - case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => - b.copy(hartId = i + up(RocketTilesKey, site).length) - } - case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) -}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 74e9a131..ee17916f 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -75,11 +75,11 @@ class SmallBaseBoomConfig extends Config( new boom.system.SmallBoomConfig) class DefaultBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new BaseBoomConfig) class SmallDefaultBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new SmallBaseBoomConfig) class HwachaBoomConfig extends Config( @@ -91,26 +91,26 @@ class RoccBoomConfig extends Config( new DefaultBoomConfig) class PWMBoomConfig extends Config( - new WithPWMBoomTop ++ + new WithPWMBoomAndRocketTop ++ new BaseBoomConfig) class PWMAXI4BoomConfig extends Config( - new WithPWMAXI4BoomTop ++ + new WithPWMAXI4BoomAndRocketTop ++ new BaseBoomConfig) class SimBlockDeviceBoomConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomTop ++ + new WithSimBlockDeviceBoomAndRocketTop ++ new BaseBoomConfig) class BlockDeviceModelBoomConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomTop ++ + new WithBlockDeviceModelBoomAndRocketTop ++ new BaseBoomConfig) class GPIOBoomConfig extends Config( new WithGPIO ++ - new WithGPIOBoomTop ++ + new WithGPIOBoomAndRocketTop ++ new BaseBoomConfig) /** @@ -118,7 +118,7 @@ class GPIOBoomConfig extends Config( * the `WithNBoomCores` with the DefaultBoomConfig params */ class DualCoreBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ @@ -127,7 +127,7 @@ class DualCoreBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreSmallBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ @@ -137,7 +137,7 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) @@ -147,7 +147,7 @@ class RV32UnifiedBoomConfig extends Config( class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(1) ++ @@ -157,7 +157,7 @@ class BaseBoomAndRocketConfig extends Config( class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.DefaultBoomConfig ++ @@ -208,7 +208,7 @@ class GPIOBoomAndRocketConfig extends Config( class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(2) ++ @@ -219,7 +219,7 @@ class DualCoreBoomAndOneRocketConfig extends Config( class RV32BoomAndRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ diff --git a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala deleted file mode 100644 index cc7fd3db..00000000 --- a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala +++ /dev/null @@ -1,62 +0,0 @@ -package example - -import chisel3._ -import chisel3.internal.sourceinfo.{SourceInfo} - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ - -import boom.system.{BoomTilesKey} - -/** - * Example top with periphery devices and ports, and a BOOM subsystem - */ -class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem - with HasAsyncExtInterrupts - with boom.system.CanHaveMisalignedMasterAXI4MemPort - with CanHaveMasterAXI4MMIOPort - with CanHaveSlaveAXI4Port - with HasPeripheryBootROM -{ - override lazy val module = new ExampleBoomAndRocketSystemModule(this) - - // The sbus masters the cbus; here we convert TL-UH -> TL-UL - sbus.crossToBus(cbus, NoCrossing) - - // The cbus masters the pbus; which might be clocked slower - cbus.crossToBus(pbus, SynchronousCrossing()) - - // The fbus masters the sbus; both are TL-UH or TL-C - FlipRendering { implicit p => - sbus.crossFromBus(fbus, SynchronousCrossing()) - } - - // The sbus masters the mbus; here we convert TL-C -> TL-UH - private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) - private val (in, out, halt) = coherenceManager(this) - if (nBanks != 0) { - sbus.coupleTo("coherence_manager") { in :*= _ } - mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } - } -} - -/** - * Example top module with periphery devices and ports, and a BOOM subsystem - */ -class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer) - with HasRTCModuleImp - with HasExtInterruptsModuleImp - with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp - with CanHaveMasterAXI4MMIOPortModuleImp - with CanHaveSlaveAXI4PortModuleImp - with HasPeripheryBootROMModuleImp - with DontTouch diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index a517b6b8..3d488c1c 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -43,41 +43,6 @@ class RocketTestHarness(implicit val p: Parameters) extends Module { io.success := dut.connectSimSerial() } -// ----------------- -// BOOM Test Harness -// ----------------- - -case object BuildBoomTop extends Field[(Clock, Bool, Parameters) => BoomTopModule[BoomTop]] - -class BoomTestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - // force Chisel to rename module - override def desiredName = "TestHarness" - - val dut = p(BuildBoomTop)(clock, reset.toBool, p) - dut.debug := DontCare - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - io.success := dut.connectSimSerial() -} - // -------------------------- // BOOM + Rocket Test Harness // -------------------------- diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 50e5d0c6..a481deef 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -71,74 +71,17 @@ class RocketTopWithGPIOModule(l: RocketTopWithGPIO) extends RocketTopModule(l) with HasPeripheryGPIOModuleImp -// ---------------------- -// BOOM Top Level Systems -// ---------------------- - -class BoomTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem - with HasNoDebug - with HasPeripherySerial { - override lazy val module = new BoomTopModule(this) -} - -class BoomTopModule[+L <: BoomTop](l: L) extends boom.system.ExampleBoomSystemModule(l) - with HasRTCModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with DontTouch - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithPWMTL(implicit p: Parameters) extends BoomTop - with HasPeripheryPWMTL { - override lazy val module = new BoomTopWithPWMTLModule(this) -} - -class BoomTopWithPWMTLModule(l: BoomTopWithPWMTL) extends BoomTopModule(l) - with HasPeripheryPWMTLModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithPWMAXI4(implicit p: Parameters) extends BoomTop - with HasPeripheryPWMAXI4 { - override lazy val module = new BoomTopWithPWMAXI4Module(this) -} - -class BoomTopWithPWMAXI4Module(l: BoomTopWithPWMAXI4) extends BoomTopModule(l) - with HasPeripheryPWMAXI4ModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithBlockDevice(implicit p: Parameters) extends BoomTop - with HasPeripheryBlockDevice { - override lazy val module = new BoomTopWithBlockDeviceModule(this) -} - -class BoomTopWithBlockDeviceModule(l: BoomTopWithBlockDevice) extends BoomTopModule(l) - with HasPeripheryBlockDeviceModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop - with HasPeripheryGPIO { - override lazy val module = new BoomTopWithGPIOModule(this) -} - -class BoomTopWithGPIOModule(l: BoomTopWithGPIO) - extends BoomTopModule(l) - with HasPeripheryGPIOModuleImp - // ------------------------------- // BOOM + Rocket Top Level Systems // ------------------------------- -class BoomAndRocketTop(implicit p: Parameters) extends ExampleBoomAndRocketSystem +class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem with HasNoDebug with HasPeripherySerial { override lazy val module = new BoomAndRocketTopModule(this) } -class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends ExampleBoomAndRocketSystemModule(l) +class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) with HasRTCModuleImp with HasNoDebugModuleImp with HasPeripherySerialModuleImp diff --git a/variables.mk b/variables.mk index 62cd35ce..fb4f3632 100644 --- a/variables.mk +++ b/variables.mk @@ -48,7 +48,7 @@ ifeq ($(SUB_PROJECT),boomexample) CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= BoomTop + TOP ?= BoomAndRocketTop endif # for a BOOM + Rocket based example system ifeq ($(SUB_PROJECT),boomrocketexample) @@ -72,7 +72,7 @@ ifeq ($(SUB_PROJECT),boom) CONFIG_PACKAGE ?= boom.system GENERATOR_PACKAGE ?= boom.system TB ?= TestDriver - TOP ?= ExampleBoomSystem + TOP ?= ExampleBoomAndRocketSystem endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) @@ -186,4 +186,3 @@ sim_vsrcs = \ # assembly/benchmark variables ######################################################################################### timeout_cycles = 10000000 -bmark_timeout_cycles = 100000000 From 9182c1394abd19858534413915052819eadb0c34 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 21:46:37 -0700 Subject: [PATCH 05/13] update boom | fix comments and remove extra code --- generators/boom | 2 +- generators/example/src/main/scala/ConfigMixins.scala | 4 ++-- generators/example/src/main/scala/Top.scala | 1 - 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/generators/boom b/generators/boom index ff8c25af..734d62c6 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit ff8c25af0b14c7eba67451f574e1ddacaaf8a5b6 +Subproject commit 734d62c6a91920f62730a4a076f8dfce29c52bf2 diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 363f0895..1380b90b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -109,9 +109,9 @@ class WithGPIORocketTop extends Config((site, here, up) => { } }) -// -------------------------------------- +// ----------------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins -// -------------------------------------- +// ----------------------------------------------- /** * Class to specify a "plain" top level BOOM + Rocket system diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index a481deef..59493492 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -82,7 +82,6 @@ class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAn } class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) - with HasRTCModuleImp with HasNoDebugModuleImp with HasPeripherySerialModuleImp with DontTouch From 612aa48e65c2441de46d87e02f8690e0e4826694 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 21:51:42 -0700 Subject: [PATCH 06/13] remove extra imports --- generators/example/src/main/scala/ConfigMixins.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 1380b90b..8e8f017b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -4,17 +4,15 @@ import chisel3._ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.{XLen, MaxHartIdBits} +import freechips.rocketchip.tile.{XLen} import testchipip._ import sifive.blocks.devices.gpio._ -import boom.system.{BoomTilesKey} - /** * TODO: Why do we need this? */ From 6d622e7555f63fed80c7ed13e778b1b903be8ebe Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 22:00:04 -0700 Subject: [PATCH 07/13] add boomrocketexample to ci --- .circleci/config.yml | 72 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index 1e5146bb..50577af7 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -161,6 +161,40 @@ jobs: paths: - "/home/riscvuser/project" + prepare-boomrocketexample: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + + - run: + name: Building the boomrocketexample subproject using Verilator + command: .circleci/do-rtl-build.sh SUB_PROJECT=boomrocketexample CONFIG=SmallDefaultBoomAndRocketConfig + no_output_timeout: 120m + + - save_cache: + key: boomrocketexample-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" + prepare-boom: docker: - image: riscvboom/riscvboom-images:0.0.5 @@ -319,6 +353,34 @@ jobs: name: Run boomexample benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig + boomrocketexample-run-benchmark-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - boomrocketexample-{{ .Branch }}-{{ .Revision }} + + - run: + name: Run boomrocketexample benchmark tests + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomAndRocketConfig + boom-run-benchmark-tests: docker: - image: riscvboom/riscvboom-images:0.0.5 @@ -427,6 +489,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-boomrocketexample: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-boom: requires: - install-riscv-toolchain @@ -456,6 +523,11 @@ workflows: - install-riscv-toolchain - prepare-boomexample + - boomrocketexample-run-benchmark-tests: + requires: + - install-riscv-toolchain + - prepare-boomrocketexample + - boom-run-benchmark-tests: requires: - install-riscv-toolchain From f071b522b2b58b4e38041aacab19ddefc554fb2e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 22:01:50 -0700 Subject: [PATCH 08/13] ci harness fix for boomexample --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index fb4f3632..16e69d02 100644 --- a/variables.mk +++ b/variables.mk @@ -41,7 +41,7 @@ endif # for a BOOM based example system ifeq ($(SUB_PROJECT),boomexample) SBT_PROJECT ?= example - MODEL ?= BoomTestHarness + MODEL ?= BoomAndRocketTestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultBoomConfig From 5408d6ecbef7c7d972ce5c3fc3417a03739faaf2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 22:58:28 -0700 Subject: [PATCH 09/13] bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 734d62c6..4b0365f4 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 734d62c6a91920f62730a4a076f8dfce29c52bf2 +Subproject commit 4b0365f4ff6eda6018b1f6fb116f54d0ace35486 From 08dd5b53758aadcc80845bba325f9fa10feea43b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 17:37:16 -0700 Subject: [PATCH 10/13] update boom to master --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 4b0365f4..92313af2 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4b0365f4ff6eda6018b1f6fb116f54d0ace35486 +Subproject commit 92313af2a0ed4d8a93591a08f42ede1a0ffd808a From c19855bfa66406186738fac9363b08f2725f5f5c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 26 May 2019 15:46:19 -0700 Subject: [PATCH 11/13] shared heter-subsystem | single example SUB_PROJECT --- .circleci/config.yml | 8 +-- .../example/src/main/scala/ConfigMixins.scala | 66 ------------------- .../example/src/main/scala/Configs.scala | 12 ++-- .../example/src/main/scala/Generator.scala | 4 ++ .../example/src/main/scala/TestHarness.scala | 38 +---------- generators/example/src/main/scala/Top.scala | 65 +----------------- variables.mk | 26 +------- 7 files changed, 20 insertions(+), 199 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 50577af7..d2354fde 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -153,7 +153,7 @@ jobs: - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig no_output_timeout: 120m - save_cache: @@ -187,7 +187,7 @@ jobs: - run: name: Building the boomrocketexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=boomrocketexample CONFIG=SmallDefaultBoomAndRocketConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig no_output_timeout: 120m - save_cache: @@ -351,7 +351,7 @@ jobs: - run: name: Run boomexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig boomrocketexample-run-benchmark-tests: docker: @@ -379,7 +379,7 @@ jobs: - run: name: Run boomrocketexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomAndRocketConfig + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig boom-run-benchmark-tests: docker: diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 8e8f017b..dbfc1c34 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -41,72 +41,6 @@ class WithGPIO extends Config((site, here, up) => { GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) }) -// ---------------------------------------- -// Rocket Top Level System Parameter Mixins -// ---------------------------------------- - -/** - * Class to specify a "plain" top level rocket-chip system - */ -class WithNormalRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new RocketTop()(p)).module) - } -}) - -/** - * Class to specify a top level rocket-chip system with PWM - */ -class WithPWMRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new RocketTopWithPWMTL()(p)).module) -}) - -/** - * Class to specify a top level rocket-chip system with a PWM AXI4 - */ -class WithPWMAXI4RocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new RocketTopWithPWMAXI4()(p)).module) -}) - -/** - * Class to specify a top level rocket-chip system with a block device - */ -class WithBlockDeviceModelRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -/** - * Class to specify a top level rocket-chip system with a simulator block device - */ -class WithSimBlockDeviceRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -/** - * Class to specify a top level rocket-chip system with GPIO - */ -class WithGPIORocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithGPIO()(p)).module) - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } -}) - // ----------------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins // ----------------------------------------------- diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index ee17916f..98a37bc7 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -16,7 +16,7 @@ class BaseRocketConfig extends Config( new freechips.rocketchip.system.DefaultConfig) class DefaultRocketConfig extends Config( - new WithNormalRocketTop ++ + new WithNormalBoomAndRocketTop ++ new BaseRocketConfig) class HwachaConfig extends Config( @@ -28,26 +28,26 @@ class RoccRocketConfig extends Config( new DefaultRocketConfig) class PWMRocketConfig extends Config( - new WithPWMRocketTop ++ + new WithPWMBoomAndRocketTop ++ new BaseRocketConfig) class PWMAXI4RocketConfig extends Config( - new WithPWMAXI4RocketTop ++ + new WithPWMAXI4BoomAndRocketTop ++ new BaseRocketConfig) class SimBlockDeviceRocketConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceRocketTop ++ + new WithSimBlockDeviceBoomAndRocketTop ++ new BaseRocketConfig) class BlockDeviceModelRocketConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelRocketTop ++ + new WithBlockDeviceModelBoomAndRocketTop ++ new BaseRocketConfig) class GPIORocketConfig extends Config( new WithGPIO ++ - new WithGPIORocketTop ++ + new WithGPIOBoomAndRocketTop ++ new BaseRocketConfig) class DualCoreRocketConfig extends Config( diff --git a/generators/example/src/main/scala/Generator.scala b/generators/example/src/main/scala/Generator.scala index 3a1300b4..c5df8cb1 100644 --- a/generators/example/src/main/scala/Generator.scala +++ b/generators/example/src/main/scala/Generator.scala @@ -1,15 +1,19 @@ package example import scala.collection.mutable.LinkedHashSet + import chisel3._ import chisel3.experimental._ + import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} + import freechips.rocketchip.subsystem.{RocketTilesKey} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.{GeneratorApp} import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} + import boom.system.{BoomTilesKey, BoomTestSuites} object Generator extends GeneratorApp { diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index 3d488c1c..7bad5cbc 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -2,47 +2,13 @@ package example import chisel3._ import chisel3.experimental._ + import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} + import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp -// ------------------- -// Rocket Test Harness -// ------------------- - -case object BuildRocketTop extends Field[(Clock, Bool, Parameters) => RocketTopModule[RocketTop]] - -class RocketTestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - // force Chisel to rename module - override def desiredName = "TestHarness" - - val dut = p(BuildRocketTop)(clock, reset.toBool, p) - dut.debug := DontCare - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - - io.success := dut.connectSimSerial() -} - // -------------------------- // BOOM + Rocket Test Harness // -------------------------- diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 59493492..ddd4a20f 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -1,76 +1,17 @@ package example import chisel3._ + import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util.DontTouch + import testchipip._ + import sifive.blocks.devices.gpio._ -// ------------------------ -// Rocket Top Level Systems -// ------------------------ - -class RocketTop(implicit p: Parameters) extends ExampleRocketSystem - with CanHaveMasterAXI4MemPort - with HasPeripheryBootROM - with HasNoDebug - with HasPeripherySerial { - override lazy val module = new RocketTopModule(this) -} - -class RocketTopModule[+L <: RocketTop](l: L) extends ExampleRocketSystemModuleImp(l) - with HasRTCModuleImp - with CanHaveMasterAXI4MemPortModuleImp - with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with DontTouch - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithPWMTL(implicit p: Parameters) extends RocketTop - with HasPeripheryPWMTL { - override lazy val module = new RocketTopWithPWMTLModule(this) -} - -class RocketTopWithPWMTLModule(l: RocketTopWithPWMTL) - extends RocketTopModule(l) with HasPeripheryPWMTLModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithPWMAXI4(implicit p: Parameters) extends RocketTop - with HasPeripheryPWMAXI4 { - override lazy val module = new RocketTopWithPWMAXI4Module(this) -} - -class RocketTopWithPWMAXI4Module(l: RocketTopWithPWMAXI4) - extends RocketTopModule(l) with HasPeripheryPWMAXI4ModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithBlockDevice(implicit p: Parameters) extends RocketTop - with HasPeripheryBlockDevice { - override lazy val module = new RocketTopWithBlockDeviceModule(this) -} - -class RocketTopWithBlockDeviceModule(l: RocketTopWithBlockDevice) - extends RocketTopModule(l) - with HasPeripheryBlockDeviceModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithGPIO(implicit p: Parameters) extends RocketTop - with HasPeripheryGPIO { - override lazy val module = new RocketTopWithGPIOModule(this) -} - -class RocketTopWithGPIOModule(l: RocketTopWithGPIO) - extends RocketTopModule(l) - with HasPeripheryGPIOModuleImp - // ------------------------------- // BOOM + Rocket Top Level Systems // ------------------------------- diff --git a/variables.mk b/variables.mk index 16e69d02..f73d7f7a 100644 --- a/variables.mk +++ b/variables.mk @@ -29,37 +29,13 @@ SUB_PROJECT ?= example ifeq ($(SUB_PROJECT),example) SBT_PROJECT ?= example - MODEL ?= RocketTestHarness + MODEL ?= BoomAndRocketTestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultRocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= RocketTop -endif -# for a BOOM based example system -ifeq ($(SUB_PROJECT),boomexample) - SBT_PROJECT ?= example - MODEL ?= BoomAndRocketTestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= DefaultBoomConfig - CONFIG_PACKAGE ?= $(SBT_PROJECT) - GENERATOR_PACKAGE ?= $(SBT_PROJECT) - TB ?= TestDriver - TOP ?= BoomAndRocketTop -endif -# for a BOOM + Rocket based example system -ifeq ($(SUB_PROJECT),boomrocketexample) - SBT_PROJECT ?= example - MODEL ?= BoomAndRocketTestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= DefaultBoomAndRocketConfig - CONFIG_PACKAGE ?= $(SBT_PROJECT) - GENERATOR_PACKAGE ?= $(SBT_PROJECT) - TB ?= TestDriver TOP ?= BoomAndRocketTop endif # for BOOM developers From ee62fa8bac1814c41d1d5481ba400d97e908f1c7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 17:21:19 -0700 Subject: [PATCH 12/13] renamed classes to BoomRocket to clarify | clearer comments | readd the bmark timeout --- .../example/src/main/scala/ConfigMixins.scala | 50 ++++++------- .../example/src/main/scala/Configs.scala | 70 +++++++++---------- .../example/src/main/scala/TestHarness.scala | 8 +-- generators/example/src/main/scala/Top.scala | 34 ++++----- variables.mk | 5 +- 5 files changed, 84 insertions(+), 83 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index dbfc1c34..f5e56411 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -42,62 +42,62 @@ class WithGPIO extends Config((site, here, up) => { }) // ----------------------------------------------- -// BOOM + Rocket Top Level System Parameter Mixins +// BOOM and/or Rocket Top Level System Parameter Mixins // ----------------------------------------------- /** - * Class to specify a "plain" top level BOOM + Rocket system + * Class to specify a "plain" top level BOOM and/or Rocket system */ -class WithNormalBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomAndRocketTop()(p)).module) +class WithNormalBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomRocketTop()(p)).module) } }) /** - * Class to specify a top level BOOM + Rocket system with PWM + * Class to specify a top level BOOM and/or Rocket system with PWM */ -class WithPWMBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomAndRocketTopWithPWMTL()(p)).module) +class WithPWMBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomRocketTopWithPWMTL()(p)).module) }) /** - * Class to specify a top level BOOM + Rocket system with a PWM AXI4 + * Class to specify a top level BOOM and/or Rocket system with a PWM AXI4 */ -class WithPWMAXI4BoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomAndRocketTopWithPWMAXI4()(p)).module) +class WithPWMAXI4BoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomRocketTopWithPWMAXI4()(p)).module) }) /** - * Class to specify a top level BOOM + Rocket system with a block device + * Class to specify a top level BOOM and/or Rocket system with a block device */ -class WithBlockDeviceModelBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) +class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module) top.connectBlockDeviceModel() top } }) /** - * Class to specify a top level BOOM + Rocket system with a simulator block device + * Class to specify a top level BOOM and/or Rocket system with a simulator block device */ -class WithSimBlockDeviceBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) +class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module) top.connectSimBlockDevice(clock, reset) top } }) /** - * Class to specify a top level BOOM + Rocket system with GPIO + * Class to specify a top level BOOM and/or Rocket system with GPIO */ -class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomAndRocketTopWithGPIO()(p)).module) +class WithGPIOBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomRocketTopWithGPIO()(p)).module) for (gpio <- top.gpio) { for (pin <- gpio.pins) { pin.i.ival := false.B diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 98a37bc7..114d8baa 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -16,7 +16,7 @@ class BaseRocketConfig extends Config( new freechips.rocketchip.system.DefaultConfig) class DefaultRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new BaseRocketConfig) class HwachaConfig extends Config( @@ -28,26 +28,26 @@ class RoccRocketConfig extends Config( new DefaultRocketConfig) class PWMRocketConfig extends Config( - new WithPWMBoomAndRocketTop ++ + new WithPWMBoomRocketTop ++ new BaseRocketConfig) class PWMAXI4RocketConfig extends Config( - new WithPWMAXI4BoomAndRocketTop ++ + new WithPWMAXI4BoomRocketTop ++ new BaseRocketConfig) class SimBlockDeviceRocketConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomAndRocketTop ++ + new WithSimBlockDeviceBoomRocketTop ++ new BaseRocketConfig) class BlockDeviceModelRocketConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomAndRocketTop ++ + new WithBlockDeviceModelBoomRocketTop ++ new BaseRocketConfig) class GPIORocketConfig extends Config( new WithGPIO ++ - new WithGPIOBoomAndRocketTop ++ + new WithGPIOBoomRocketTop ++ new BaseRocketConfig) class DualCoreRocketConfig extends Config( @@ -75,11 +75,11 @@ class SmallBaseBoomConfig extends Config( new boom.system.SmallBoomConfig) class DefaultBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new BaseBoomConfig) class SmallDefaultBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new SmallBaseBoomConfig) class HwachaBoomConfig extends Config( @@ -91,26 +91,26 @@ class RoccBoomConfig extends Config( new DefaultBoomConfig) class PWMBoomConfig extends Config( - new WithPWMBoomAndRocketTop ++ + new WithPWMBoomRocketTop ++ new BaseBoomConfig) class PWMAXI4BoomConfig extends Config( - new WithPWMAXI4BoomAndRocketTop ++ + new WithPWMAXI4BoomRocketTop ++ new BaseBoomConfig) class SimBlockDeviceBoomConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomAndRocketTop ++ + new WithSimBlockDeviceBoomRocketTop ++ new BaseBoomConfig) class BlockDeviceModelBoomConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomAndRocketTop ++ + new WithBlockDeviceModelBoomRocketTop ++ new BaseBoomConfig) class GPIOBoomConfig extends Config( new WithGPIO ++ - new WithGPIOBoomAndRocketTop ++ + new WithGPIOBoomRocketTop ++ new BaseBoomConfig) /** @@ -118,7 +118,7 @@ class GPIOBoomConfig extends Config( * the `WithNBoomCores` with the DefaultBoomConfig params */ class DualCoreBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ @@ -127,7 +127,7 @@ class DualCoreBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreSmallBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ @@ -137,12 +137,12 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) // --------------------- -// BOOM + Rocket Configs +// BOOM and Rocket Configs // --------------------- class BaseBoomAndRocketConfig extends Config( @@ -167,46 +167,46 @@ class SmallBaseBoomAndRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DefaultBoomAndRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithNormalBoomRocketTop ++ + new BaseBoomRocketConfig) class SmallDefaultBoomAndRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ - new SmallBaseBoomAndRocketConfig) + new WithNormalBoomRocketTop ++ + new SmallBaseBoomRocketConfig) class HwachaBoomAndRocketConfig extends Config( new hwacha.DefaultHwachaConfig ++ - new DefaultBoomAndRocketConfig) + new DefaultBoomRocketConfig) class RoccBoomAndRocketConfig extends Config( new WithRoccExample ++ - new DefaultBoomAndRocketConfig) + new DefaultBoomRocketConfig) class PWMBoomAndRocketConfig extends Config( - new WithPWMBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithPWMBoomRocketTop ++ + new BaseBoomRocketConfig) class PWMAXI4BoomAndRocketConfig extends Config( - new WithPWMAXI4BoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithPWMAXI4BoomRocketTop ++ + new BaseBoomRocketConfig) class SimBlockDeviceBoomAndRocketConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithSimBlockDeviceBoomRocketTop ++ + new BaseBoomRocketConfig) class BlockDeviceModelBoomAndRocketConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithBlockDeviceModelBoomRocketTop ++ + new BaseBoomRocketConfig) class GPIOBoomAndRocketConfig extends Config( new WithGPIO ++ - new WithGPIOBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithGPIOBoomRocketTop ++ + new BaseBoomRocketConfig) class DualCoreBoomAndOneRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ @@ -217,7 +217,7 @@ class DualCoreBoomAndOneRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32BoomAndRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index 7bad5cbc..c59a081e 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -10,12 +10,12 @@ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp // -------------------------- -// BOOM + Rocket Test Harness +// BOOM and/or Rocket Test Harness // -------------------------- -case object BuildBoomAndRocketTop extends Field[(Clock, Bool, Parameters) => BoomAndRocketTopModule[BoomAndRocketTop]] +case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]] -class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { +class BoomRocketTestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) @@ -23,7 +23,7 @@ class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { // force Chisel to rename module override def desiredName = "TestHarness" - val dut = p(BuildBoomAndRocketTop)(clock, reset.toBool, p) + val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p) dut.debug := DontCare dut.connectSimAXIMem() dut.connectSimAXIMMIO() diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index ddd4a20f..5ee73906 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -13,57 +13,57 @@ import testchipip._ import sifive.blocks.devices.gpio._ // ------------------------------- -// BOOM + Rocket Top Level Systems +// BOOM and/or Rocket Top Level Systems // ------------------------------- -class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem +class BoomRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem with HasNoDebug with HasPeripherySerial { - override lazy val module = new BoomAndRocketTopModule(this) + override lazy val module = new BoomRocketTopModule(this) } -class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) +class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) with HasNoDebugModuleImp with HasPeripherySerialModuleImp with DontTouch //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithPWMTL(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithPWMTL(implicit p: Parameters) extends BoomRocketTop with HasPeripheryPWMTL { - override lazy val module = new BoomAndRocketTopWithPWMTLModule(this) + override lazy val module = new BoomRocketTopWithPWMTLModule(this) } -class BoomAndRocketTopWithPWMTLModule(l: BoomAndRocketTopWithPWMTL) extends BoomAndRocketTopModule(l) +class BoomRocketTopWithPWMTLModule(l: BoomRocketTopWithPWMTL) extends BoomRocketTopModule(l) with HasPeripheryPWMTLModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomRocketTop with HasPeripheryPWMAXI4 { - override lazy val module = new BoomAndRocketTopWithPWMAXI4Module(this) + override lazy val module = new BoomRocketTopWithPWMAXI4Module(this) } -class BoomAndRocketTopWithPWMAXI4Module(l: BoomAndRocketTopWithPWMAXI4) extends BoomAndRocketTopModule(l) +class BoomRocketTopWithPWMAXI4Module(l: BoomRocketTopWithPWMAXI4) extends BoomRocketTopModule(l) with HasPeripheryPWMAXI4ModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithBlockDevice(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithBlockDevice(implicit p: Parameters) extends BoomRocketTop with HasPeripheryBlockDevice { - override lazy val module = new BoomAndRocketTopWithBlockDeviceModule(this) + override lazy val module = new BoomRocketTopWithBlockDeviceModule(this) } -class BoomAndRocketTopWithBlockDeviceModule(l: BoomAndRocketTopWithBlockDevice) extends BoomAndRocketTopModule(l) +class BoomRocketTopWithBlockDeviceModule(l: BoomRocketTopWithBlockDevice) extends BoomRocketTopModule(l) with HasPeripheryBlockDeviceModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithGPIO(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop with HasPeripheryGPIO { - override lazy val module = new BoomAndRocketTopWithGPIOModule(this) + override lazy val module = new BoomRocketTopWithGPIOModule(this) } -class BoomAndRocketTopWithGPIOModule(l: BoomAndRocketTopWithGPIO) - extends BoomAndRocketTopModule(l) +class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO) + extends BoomRocketTopModule(l) with HasPeripheryGPIOModuleImp diff --git a/variables.mk b/variables.mk index f73d7f7a..7545e9a3 100644 --- a/variables.mk +++ b/variables.mk @@ -29,14 +29,14 @@ SUB_PROJECT ?= example ifeq ($(SUB_PROJECT),example) SBT_PROJECT ?= example - MODEL ?= BoomAndRocketTestHarness + MODEL ?= BoomRocketTestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultRocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= BoomAndRocketTop + TOP ?= BoomRocketTop endif # for BOOM developers ifeq ($(SUB_PROJECT),boom) @@ -162,3 +162,4 @@ sim_vsrcs = \ # assembly/benchmark variables ######################################################################################### timeout_cycles = 10000000 +bmark_timeout_cycles = 100000000 From 540afea07aef44b7e8b2614c397659ba66908232 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 19:12:07 -0700 Subject: [PATCH 13/13] fix config naming --- .../example/src/main/scala/Configs.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 114d8baa..edf1be75 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -168,42 +168,42 @@ class SmallBaseBoomAndRocketConfig extends Config( class DefaultBoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class SmallDefaultBoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ - new SmallBaseBoomRocketConfig) + new SmallBaseBoomAndRocketConfig) class HwachaBoomAndRocketConfig extends Config( new hwacha.DefaultHwachaConfig ++ - new DefaultBoomRocketConfig) + new DefaultBoomAndRocketConfig) class RoccBoomAndRocketConfig extends Config( new WithRoccExample ++ - new DefaultBoomRocketConfig) + new DefaultBoomAndRocketConfig) class PWMBoomAndRocketConfig extends Config( new WithPWMBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class PWMAXI4BoomAndRocketConfig extends Config( new WithPWMAXI4BoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class SimBlockDeviceBoomAndRocketConfig extends Config( new WithBlockDevice ++ new WithSimBlockDeviceBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class BlockDeviceModelBoomAndRocketConfig extends Config( new WithBlockDevice ++ new WithBlockDeviceModelBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class GPIOBoomAndRocketConfig extends Config( new WithGPIO ++ new WithGPIOBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomRocketTop ++