Merge remote-tracking branch 'origin/main' into cospike-integration

generators/chipyard/src/main/resources/vsrc/spiketile.v

@@ -286,10 +286,10 @@ module SpikeBlackBox #(
    wire                                                    __tcm_d_ready;
    bit                                                     __tcm_d_valid;
    longint                                                 __tcm_d_data;
-   
+
    reg                                                     __tcm_d_valid_reg;
    reg [63:0]                                              __tcm_d_data_reg;
-   
+
 
 
    always @(posedge clock) begin
@@ -429,7 +429,7 @@ module SpikeBlackBox #(
 
          __tcm_d_valid_reg <= __tcm_d_valid;
          __tcm_d_data_reg <= __tcm_d_data;
-         
+
       end
    end // always @ (posedge clock)
    assign insns_retired = __insns_retired_reg;

generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala

@@ -91,4 +91,3 @@ class SimplePllConfiguration(
    }
    def referenceSinkParams(): ClockSinkParameters = sinkDividerMap.find(_._2 == 1).get._1
 }
-

generators/chipyard/src/main/scala/clocking/TileClockGater.scala

@@ -45,4 +45,3 @@ class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, va
     }): _*)
   }
 }
-

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -67,4 +67,3 @@ class dmiMediumBoomCosimConfig extends Config(
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
   new boom.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)
-

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -92,4 +92,3 @@ class UARTTSIRocketConfig extends Config(
   new chipyard.config.WithPeripheryBusFrequency(10) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
-

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -23,7 +23,7 @@ import chipyard.{ExtTLMem}
 
 /**
   * Config fragment for adding a BootROM to the SoC
-  * 
+  *
   * @param address the address of the BootROM device
   * @param size the size of the BootROM
   * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset
@@ -42,7 +42,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt =
 // DOC include start: gpio config fragment
 /**
  * Config fragment for adding a GPIO peripheral device to the SoC
- * 
+ *
  * @param address the address of the GPIO device
  * @param width the number of pins of the GPIO device
  */

generators/chipyard/src/main/scala/stage/ChipyardOptions.scala

@@ -38,4 +38,3 @@ class ChipyardOptions private[stage] (
       if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None
   }
 }
-