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fixup! Update MacroCompiler for Chisel 3.4

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Need to collect the annotations into a Seq.
Also updated the macros project tests.
This commit is contained in:
Tim Snyder
2020-10-23 18:02:35 +00:00
parent aca4bd579f
commit 446cb84cbf
2 changed files with 4 additions and 4 deletions
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2
macros/src/main/scala/MacroCompiler.scala
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@@ -656,7 +656,7 @@ class MacroCompilerTransform extends Transform {
def inputForm = MidForm def inputForm = MidForm
def outputForm = MidForm def outputForm = MidForm
def execute(state: CircuitState) = state.annotations match { def execute(state: CircuitState) = state.annotations.collect { case a: MacroCompilerAnnotation => a } match {
case Seq(anno: MacroCompilerAnnotation) => case Seq(anno: MacroCompilerAnnotation) =>
val MacroCompilerAnnotation.Params(memFile, memFileFormat, libFile, hammerIR, costMetric, mode, useCompiler, forceCompile, forceSynflops) = anno.params val MacroCompilerAnnotation.Params(memFile, memFileFormat, libFile, hammerIR, costMetric, mode, useCompiler, forceCompile, forceSynflops) = anno.params
if (mode == MacroCompilerAnnotation.FallbackSynflops) { if (mode == MacroCompilerAnnotation.FallbackSynflops) {

6
macros/src/test/scala/MacroCompilerSpec.scala
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@@ -3,7 +3,7 @@ package barstools.macros
import firrtl.ir.{Circuit, NoInfo} import firrtl.ir.{Circuit, NoInfo}
import firrtl.passes.RemoveEmpty import firrtl.passes.RemoveEmpty
import firrtl.Parser.parse import firrtl.Parser.parse
import firrtl.Utils.ceilLog2 import firrtl.Utils.getUIntWidth
import java.io.{File, StringWriter} import java.io.{File, StringWriter}
import mdf.macrolib.SRAMMacro import mdf.macrolib.SRAMMacro
@@ -247,10 +247,10 @@ trait HasSimpleTestGenerator {
val v = s"${generatorType}${extraTagPrefixed}.v" val v = s"${generatorType}${extraTagPrefixed}.v"
lazy val mem_name = "target_memory" lazy val mem_name = "target_memory"
val mem_addr_width = ceilLog2(memDepth) val mem_addr_width = getUIntWidth(memDepth-1)
lazy val lib_name = "awesome_lib_mem" lazy val lib_name = "awesome_lib_mem"
val lib_addr_width = ceilLog2(libDepth) val lib_addr_width = getUIntWidth(libDepth-1)
// Override these to change the port prefixes if needed. // Override these to change the port prefixes if needed.
def libPortPrefix: String = "lib" def libPortPrefix: String = "lib"