From ae6bd057b6d77bd1aae0fd855370902d73d1914b Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 4 Dec 2023 02:32:31 -0800 Subject: [PATCH 1/7] FIX: change default UART fifo depth --- .../main/scala/config/fragments/PeripheralFragments.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 51d31094..a5e7eddf 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -65,11 +65,12 @@ class WithNoUART extends Config((site, here, up) => { * @param address the address of the UART device * @param baudrate the baudrate of the UART device */ -class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000) extends Config ((site, here, up) => { +class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000, txEntries: Int = 8, rxEntries: Int = 8) extends Config ((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq( - UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) + UARTParams(address = address, nTxEntries = txEntries, nRxEntries = rxEntries, initBaudRate = baudrate)) }) +// @deprecated("Use WithUART instead of WithUARTFIFOEntries", "chipyard v1.10") class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries)) }) From 52a98f1fb584f12b75a4a275aae53e185fc7b493 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 4 Dec 2023 02:32:53 -0800 Subject: [PATCH 2/7] ADD: update Spike UART configs --- .../chipyard/src/main/scala/config/SpikeConfigs.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index 4c1fc303..9153d05b 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -18,7 +18,7 @@ class dmiSpikeConfig extends Config( // Avoids polling on the UART registers class SpikeFastUARTConfig extends Config( new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.WithUARTFIFOEntries(128, 128) ++ + new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.AbstractConfig) @@ -27,7 +27,7 @@ class SpikeFastUARTConfig extends Config( class SpikeUltraFastConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.WithUARTFIFOEntries(128, 128) ++ + new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.WithBroadcastManager ++ @@ -47,7 +47,7 @@ class SpikeUltraFastDevicesConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.WithUARTFIFOEntries(128, 128) ++ + new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.WithBroadcastManager ++ From cd84d9e866fe04c4ec4baad545d17803bf9e30a6 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Sun, 17 Dec 2023 21:47:37 -0800 Subject: [PATCH 3/7] FIX: remove default UART and add new with desired parameters --- generators/chipyard/src/main/scala/config/SpikeConfigs.scala | 3 +++ 1 file changed, 3 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index 9153d05b..6b3e1244 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -18,6 +18,7 @@ class dmiSpikeConfig extends Config( // Avoids polling on the UART registers class SpikeFastUARTConfig extends Config( new chipyard.WithNSpikeCores(1) ++ + new chipyard.config.WithNoUART() ++ new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ @@ -27,6 +28,7 @@ class SpikeFastUARTConfig extends Config( class SpikeUltraFastConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ + new chipyard.config.WithNoUART() ++ new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ @@ -47,6 +49,7 @@ class SpikeUltraFastDevicesConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ + new chipyard.config.WithNoUART() ++ new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ From af87056768b447e34344650e2599e58e26b7dc88 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 18 Dec 2023 13:29:13 -0800 Subject: [PATCH 4/7] FIX: fix the order of the UART fragments --- .../chipyard/src/main/scala/config/SpikeConfigs.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index 6b3e1244..d221b41c 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -18,8 +18,8 @@ class dmiSpikeConfig extends Config( // Avoids polling on the UART registers class SpikeFastUARTConfig extends Config( new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.WithNoUART() ++ new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ + new chipyard.config.WithNoUART() ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.AbstractConfig) @@ -28,8 +28,8 @@ class SpikeFastUARTConfig extends Config( class SpikeUltraFastConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.WithNoUART() ++ new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ + new chipyard.config.WithNoUART() ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.WithBroadcastManager ++ @@ -49,8 +49,8 @@ class SpikeUltraFastDevicesConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.WithNoUART() ++ new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ + new chipyard.config.WithNoUART() ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.WithBroadcastManager ++ From b3c97868e106536eda5d28480b83c23a5feea089 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 18 Dec 2023 13:57:36 -0800 Subject: [PATCH 5/7] ADD: add inline comment for UART --- .../src/main/scala/config/SpikeConfigs.scala | 12 ++++++------ .../firechip/src/main/scala/TargetConfigs.scala | 3 +++ 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index d221b41c..ba7a1fb2 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -18,8 +18,8 @@ class dmiSpikeConfig extends Config( // Avoids polling on the UART registers class SpikeFastUARTConfig extends Config( new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ - new chipyard.config.WithNoUART() ++ + new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer, + new chipyard.config.WithNoUART() ++ // so we overwrite the default one new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.AbstractConfig) @@ -28,8 +28,8 @@ class SpikeFastUARTConfig extends Config( class SpikeUltraFastConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ - new chipyard.config.WithNoUART() ++ + new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer, + new chipyard.config.WithNoUART() ++ // so we overwrite the default one new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.WithBroadcastManager ++ @@ -49,8 +49,8 @@ class SpikeUltraFastDevicesConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ - new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ - new chipyard.config.WithNoUART() ++ + new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer, + new chipyard.config.WithNoUART() ++ // so we overwrite the default one new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ new chipyard.config.WithBroadcastManager ++ diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 944fe9cf..67313b08 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -135,6 +135,9 @@ class WithFireSimHighPerfClocking extends Config( // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz class WithFireSimConfigTweaks extends Config( + new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // FireSim requires a larger UART FIFO buffer, + new chipyard.config.WithNoUART() ++ // so we overwrite the default one + // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency) // Using some other frequency will require runnings the FASED runtime configuration generator // to generate faithful DDR3 timing values. From 5db66116286254dff359f798b9a20c62353a30cf Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 6 Mar 2024 00:02:42 -0800 Subject: [PATCH 6/7] FIX: Update UART FIFO depth --- generators/firechip/src/main/scala/TargetConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 7a6d1e66..5b3fef0a 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -136,7 +136,7 @@ class WithFireSimHighPerfClocking extends Config( // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz class WithFireSimConfigTweaks extends Config( - new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // FireSim requires a larger UART FIFO buffer, + new chipyard.config.WithUART(txEntries=256, rxEntries=256) ++ // FireSim requires a larger UART FIFO buffer, new chipyard.config.WithNoUART() ++ // so we overwrite the default one // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency) From 55ceca8f4588b00784ebb19342036e17b05f0f9e Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 6 Mar 2024 13:23:19 -0800 Subject: [PATCH 7/7] REFACTOR: change per Abe's request --- generators/firechip/src/main/scala/TargetConfigs.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 5b3fef0a..483afb7b 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -104,7 +104,10 @@ class WithFireSimDesignTweaks extends Config( // Optional: reduce the width of the Serial TL interface new testchipip.serdes.WithSerialTLWidth(4) ++ // Required*: Scale default baud rate with periphery bus frequency - new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ + new chipyard.config.WithUART( + baudrate=BigInt(3686400L), + txEntries=256, rxEntries=256) ++ // FireSim requires a larger UART FIFO buffer, + new chipyard.config.WithNoUART() ++ // so we overwrite the default one // Optional: Adds IO to attach tracerV bridges new chipyard.config.WithTraceIO ++ // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1) @@ -136,9 +139,6 @@ class WithFireSimHighPerfClocking extends Config( // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz class WithFireSimConfigTweaks extends Config( - new chipyard.config.WithUART(txEntries=256, rxEntries=256) ++ // FireSim requires a larger UART FIFO buffer, - new chipyard.config.WithNoUART() ++ // so we overwrite the default one - // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency) // Using some other frequency will require runnings the FASED runtime configuration generator // to generate faithful DDR3 timing values.