From 427082ba7096a9d9cc2ad90c96faeaa39bdfac01 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Sun, 6 Oct 2019 14:28:03 -0700 Subject: [PATCH] [skip ci] address John's comments --- docs/VLSI/Tutorial.rst | 6 +++--- vlsi/example.yml | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index de6e0166..db1cee60 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -54,7 +54,7 @@ Prerequisites * Genus, Innovus, and Calibre licenses * For ASAP7 specifically: - * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin will extract and setup the PDK for you into a cache directory. + * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you. * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion. * Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded). @@ -84,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB -The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. Note this will dramatically increase synthesis runtimes if your design has a lot of caches. +The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches). The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module. @@ -99,7 +99,7 @@ example-vlsi ^^^^^^^^^^^^ This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. -The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter. This hook is run after ``write_design`` because the ASAP7 PDK requires post-par GDSs to be scaled down by a factor of 4. +The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter, and should be inserted after ``write_design``. This hook is necessary because the ASAP7 PDK does place-and-route using 4x upscaled LEFs for Innovus licensing reasons, thereby requiring the cells created in the post-P&R GDS to be scaled down by a factor of 4. example.yml ^^^^^^^^^^^ diff --git a/vlsi/example.yml b/vlsi/example.yml index 024e844f..c8e4a72b 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -38,6 +38,7 @@ par.generate_power_straps_options: - M9 track_width: 7 # minimum allowed for M2 & M3 track_spacing: 0 + track_spacing_M3: 1 # to avoid M2 shorts at higher density track_start: 10 power_utilization: 0.05 power_utilization_M8: 1.0