Bump boom

.github/scripts/defaults.sh

@@ -28,11 +28,11 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 
 # key value store to get the build groups
 declare -A grouping
-grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
+grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
 grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
 grouping["group-constellation"]="chipyard-constellation"
-grouping["group-tracegen"]="tracegen tracegen-boom"
+grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
 grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
 grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
 
@@ -47,8 +47,10 @@ mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
 mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig"
 mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig verilog"
 mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
-mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig"
+mapping["chipyard-boomv3"]=" CONFIG=MediumBoomV3CosimConfig"
-mapping["chipyard-dmiboom"]=" CONFIG=dmiMediumBoomCosimConfig"
+mapping["chipyard-dmiboomv3"]=" CONFIG=dmiMediumBoomV3CosimConfig"
+mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
+mapping["chipyard-dmiboomv4"]=" CONFIG=dmiMediumBoomV4CosimConfig"
 mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
 mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
@@ -60,10 +62,11 @@ mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness
 mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
 mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
 mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig"
-mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
+mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomV3Config verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
-mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
+mapping["tracegen-boomv3"]=" CONFIG=BoomV3TraceGenConfig"
+mapping["tracegen-boomv4"]=" CONFIG=BoomV4TraceGenConfig"
 mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
 mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig"
 mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"

.github/scripts/run-tests.sh

@@ -46,13 +46,21 @@ case $1 in
         $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
         run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
         ;;
-    chipyard-boom)
+    chipyard-boomv3)
+        run_bmark
+        ;;
+    chipyard-boomv4)
         run_bmark
         ;;
     chipyard-shuttle)
         run_bmark ${mapping[$1]}
         ;;
-    chipyard-dmiboom)
+    chipyard-dmiboomv3)
+        # Test checkpoint-restore
+        $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
+        run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
+        ;;
+    chipyard-dmiboomv4)
         # Test checkpoint-restore
         $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
         run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
@@ -129,7 +137,10 @@ case $1 in
     tracegen)
         run_tracegen
         ;;
-    tracegen-boom)
+    tracegen-boomv3)
+        run_tracegen
+        ;;
+    tracegen-boomv4)
         run_tracegen
         ;;
     chipyard-cva6)

.github/workflows/chipyard-run-tests.yml

@@ -455,8 +455,8 @@ jobs:
           group-key: "group-cores"
           project-key: "chipyard-hetero"
 
-  chipyard-boom-run-tests:
+  chipyard-boomv3-run-tests:
-    name: chipyard-boom-run-tests
+    name: chipyard-boomv3-run-tests
     needs: prepare-chipyard-cores
     runs-on: as4
     steps:
@@ -476,7 +476,30 @@ jobs:
         uses: ./.github/actions/run-tests
         with:
           group-key: "group-cores"
-          project-key: "chipyard-boom"
+          project-key: "chipyard-boomv3"
+
+  chipyard-boomv4-run-tests:
+    name: chipyard-boomv4-run-tests
+    needs: prepare-chipyard-cores
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-cores"
+          project-key: "chipyard-boomv4"
 
   chipyard-shuttle-run-tests:
     name: chipyard-shuttle-run-tests
@@ -616,8 +639,8 @@ jobs:
           group-key: "group-peripherals"
           project-key: "chipyard-dmirocket"
 
-  chipyard-dmiboom-run-tests:
+  chipyard-dmiboomv3-run-tests:
-    name: chipyard-dmiboom-run-tests
+    name: chipyard-dmiboomv3-run-tests
     needs: prepare-chipyard-peripherals
     runs-on: as4
     steps:
@@ -637,7 +660,30 @@ jobs:
         uses: ./.github/actions/run-tests
         with:
           group-key: "group-peripherals"
-          project-key: "chipyard-dmiboom"
+          project-key: "chipyard-dmiboomv3"
+
+  chipyard-dmiboomv4-run-tests:
+    name: chipyard-dmiboomv4-run-tests
+    needs: prepare-chipyard-peripherals
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-peripherals"
+          project-key: "chipyard-dmiboomv4"
 
   chipyard-spiflashwrite-run-tests:
     name: chipyard-spiflashwrite-run-tests
@@ -870,8 +916,8 @@ jobs:
           project-key: "chipyard-mempress"
 
 
-  tracegen-boom-run-tests:
+  tracegen-boomv3-run-tests:
-    name: tracegen-boom-run-tests
+    name: tracegen-boomv3-run-tests
     needs: prepare-chipyard-tracegen
     runs-on: as4
     steps:
@@ -891,7 +937,30 @@ jobs:
         uses: ./.github/actions/run-tests
         with:
           group-key: "group-tracegen"
-          project-key: "tracegen-boom"
+          project-key: "tracegen-boomv3"
+
+  tracegen-boomv4-run-tests:
+    name: tracegen-boomv4-run-tests
+    needs: prepare-chipyard-tracegen
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-tracegen"
+          project-key: "tracegen-boomv4"
 
   tracegen-run-tests:
     name: tracegen-run-tests
@@ -1107,12 +1176,14 @@ jobs:
             documentation-check,
             chipyard-rocket-run-tests,
             chipyard-hetero-run-tests,
-            chipyard-boom-run-tests,
+            chipyard-boomv3-run-tests,
+            chipyard-boomv4-run-tests,
             chipyard-shuttle-run-tests,
             chipyard-cva6-run-tests,
             chipyard-ibex-run-tests,
             chipyard-sodor-run-tests,
-            chipyard-dmiboom-run-tests,
+            chipyard-dmiboomv3-run-tests,
+            chipyard-dmiboomv4-run-tests,
             chipyard-dmirocket-run-tests,
             chipyard-spiflashwrite-run-tests,
             chipyard-manyperipherals-run-tests,
@@ -1125,7 +1196,8 @@ jobs:
             chipyard-prefetchers-run-tests,
             chipyard-mempress-run-tests,
             chipyard-constellation-run-tests,
-            tracegen-boom-run-tests,
+            tracegen-boomv3-run-tests,
+            tracegen-boomv4-run-tests,
             tracegen-run-tests,
             icenet-run-tests,
             testchipip-run-tests,

docs/Simulation/FPGA-Accelerated-Simulation.rst

@@ -49,7 +49,7 @@ A FireSim simulation requires 3 additional config fragments:
 
 
 The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme.
-After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/config_build_recipes.yaml``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
+After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/config_build_recipes.yaml``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomV3Config`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomV3Config``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
 
 An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments.
 We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``.

fpga/src/main/scala/vc707/Configs.scala

@@ -72,7 +72,7 @@ class RocketVC707Config extends Config (
 class BoomVC707Config extends Config (
   new WithFPGAFrequency(50) ++
   new WithVC707Tweaks ++
-  new chipyard.MegaBoomConfig
+  new chipyard.MegaBoomV3Config
 )
 
 class WithFPGAFrequency(fMHz: Double) extends Config (

fpga/src/main/scala/vcu118/Configs.scala

@@ -72,7 +72,7 @@ class RocketVCU118Config extends Config(
 class BoomVCU118Config extends Config(
   new WithFPGAFrequency(50) ++
   new WithVCU118Tweaks ++
-  new chipyard.MegaBoomConfig
+  new chipyard.MegaBoomV3Config
 )
 
 class WithFPGAFrequency(fMHz: Double) extends Config(

generators/chipyard/src/main/scala/Subsystem.scala

@@ -20,9 +20,6 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.axi4._
 
-import boom.common.{BoomTile}
-
-
 import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
 
 trait CanHaveHTIF { this: BaseSubsystem =>
@@ -83,7 +80,8 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
 {
   def coreMonitorBundles = totalTiles.values.map {
     case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
-    case b: BoomTile => b.module.core.coreMonitorBundle
+    case b: boom.v3.common.BoomTile => b.module.core.coreMonitorBundle
+    case b: boom.v4.common.BoomTile => b.module.core.coreMonitorBundle
   }.toList
 
   // No-tile configs have to be handled specially.

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -3,60 +3,116 @@ package chipyard
 import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
-// BOOM Configs
+// BOOM V3 Configs
+// Performant, stable baseline
 // ---------------------
 
-class SmallBoomConfig extends Config(
+class SmallBoomV3Config extends Config(
-  new boom.common.WithNSmallBooms(1) ++                          // small boom config
+  new boom.v3.common.WithNSmallBooms(1) ++                          // small boom config
   new chipyard.config.AbstractConfig)
 
-class MediumBoomConfig extends Config(
+class MediumBoomV3Config extends Config(
-  new boom.common.WithNMediumBooms(1) ++                         // medium boom config
+  new boom.v3.common.WithNMediumBooms(1) ++                         // medium boom config
   new chipyard.config.AbstractConfig)
 
-class LargeBoomConfig extends Config(
+class LargeBoomV3Config extends Config(
-  new boom.common.WithNLargeBooms(1) ++                          // large boom config
+  new boom.v3.common.WithNLargeBooms(1) ++                          // large boom config
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class MegaBoomConfig extends Config(
+class MegaBoomV3Config extends Config(
-  new boom.common.WithNMegaBooms(1) ++                           // mega boom config
+  new boom.v3.common.WithNMegaBooms(1) ++                           // mega boom config
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class DualSmallBoomConfig extends Config(
+class DualSmallBoomV3Config extends Config(
-  new boom.common.WithNSmallBooms(2) ++                          // 2 boom cores
+  new boom.v3.common.WithNSmallBooms(2) ++                          // 2 boom cores
   new chipyard.config.AbstractConfig)
 
-class Cloned64MegaBoomConfig extends Config(
+class Cloned64MegaBoomV3Config extends Config(
-  new boom.common.WithCloneBoomTiles(63, 0) ++
+  new boom.v3.common.WithCloneBoomTiles(63, 0) ++
-  new boom.common.WithNMegaBooms(1) ++                           // mega boom config
+  new boom.v3.common.WithNMegaBooms(1) ++                           // mega boom config
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class LoopbackNICLargeBoomConfig extends Config(
+class LoopbackNICLargeBoomV3Config extends Config(
   new chipyard.harness.WithLoopbackNIC ++                        // drive NIC IOs with loopback
   new icenet.WithIceNIC ++                                       // build a NIC
-  new boom.common.WithNLargeBooms(1) ++
+  new boom.v3.common.WithNLargeBooms(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
-class MediumBoomCosimConfig extends Config(
+class MediumBoomV3CosimConfig extends Config(
   new chipyard.harness.WithCospike ++                            // attach spike-cosim
   new chipyard.config.WithTraceIO ++                             // enable the traceio
-  new boom.common.WithNMediumBooms(1) ++
+  new boom.v3.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)
 
-class dmiMediumBoomConfig extends Config(
+class dmiMediumBoomV3Config extends Config(
   new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
-  new boom.common.WithNMediumBooms(1) ++
+  new boom.v3.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)
 
-class dmiMediumBoomCosimConfig extends Config(
+class dmiMediumBoomV3CosimConfig extends Config(
   new chipyard.harness.WithCospike ++                            // attach spike-cosim
   new chipyard.config.WithTraceIO ++                             // enable the traceio
   new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anythint to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
-  new boom.common.WithNMediumBooms(1) ++
+  new boom.v3.common.WithNMediumBooms(1) ++
+  new chipyard.config.AbstractConfig)
+
+
+// ---------------------
+// BOOM V4 Configs
+// Less stable and performant, but with more advanced micro-architecture
+// Use for PD exploration
+// ---------------------
+
+class SmallBoomV4Config extends Config(
+  new boom.v4.common.WithNSmallBooms(1) ++                          // small boom config
+  new chipyard.config.AbstractConfig)
+
+class MediumBoomV4Config extends Config(
+  new boom.v4.common.WithNMediumBooms(1) ++                         // medium boom config
+  new chipyard.config.AbstractConfig)
+
+class LargeBoomV4Config extends Config(
+  new boom.v4.common.WithNLargeBooms(1) ++                          // large boom config
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new chipyard.config.AbstractConfig)
+
+class MegaBoomV4Config extends Config(
+  new boom.v4.common.WithNMegaBooms(1) ++                           // mega boom config
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new chipyard.config.AbstractConfig)
+
+class DualSmallBoomV4Config extends Config(
+  new boom.v4.common.WithNSmallBooms(2) ++                          // 2 boom cores
+  new chipyard.config.AbstractConfig)
+
+class Cloned64MegaBoomV4Config extends Config(
+  new boom.v4.common.WithCloneBoomTiles(63, 0) ++
+  new boom.v4.common.WithNMegaBooms(1) ++                           // mega boom config
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new chipyard.config.AbstractConfig)
+
+class MediumBoomV4CosimConfig extends Config(
+  new chipyard.harness.WithCospike ++                            // attach spike-cosim
+  new chipyard.config.WithTraceIO ++                             // enable the traceio
+  new boom.v4.common.WithNMediumBooms(1) ++
+  new chipyard.config.AbstractConfig)
+
+class dmiMediumBoomV4Config extends Config(
+  new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
+  new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
+  new boom.v4.common.WithNMediumBooms(1) ++
+  new chipyard.config.AbstractConfig)
+
+class dmiMediumBoomV4CosimConfig extends Config(
+  new chipyard.harness.WithCospike ++                            // attach spike-cosim
+  new chipyard.config.WithTraceIO ++                             // enable the traceio
+  new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anythint to serial-tl
+  new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
+  new boom.v4.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.{Config}
 // ---------------------
 
 class LargeBoomAndRocketConfig extends Config(
-  new boom.common.WithNLargeBooms(1) ++                          // single-core boom
+  new boom.v3.common.WithNLargeBooms(1) ++                          // single-core boom
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
@@ -16,7 +16,7 @@ class LargeBoomAndRocketConfig extends Config(
 class HwachaLargeBoomAndHwachaRocketConfig extends Config(
   new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                          // add hwacha to all harts
-  new boom.common.WithNLargeBooms(1) ++                      // add 1 boom core
+  new boom.v3.common.WithNLargeBooms(1) ++                      // add 1 boom core
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++     // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
@@ -26,7 +26,7 @@ class LargeBoomAndHwachaRocketConfig extends Config(
   new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
   new chipyard.config.WithMultiRoCCHwacha(0) ++                         // put hwacha on hart-0 (rocket)
   new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.common.WithNLargeBooms(1) ++                                 // add 1 boom core
+  new boom.v3.common.WithNLargeBooms(1) ++                                 // add 1 boom core
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
@@ -36,21 +36,21 @@ class DualLargeBoomAndHwachaRocketConfig extends Config(
   new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
   new chipyard.config.WithMultiRoCCHwacha(0) ++                         // put hwacha on hart-0 (rocket)
   new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.common.WithNLargeBooms(2) ++                                 // add 2 boom cores
+  new boom.v3.common.WithNLargeBooms(2) ++                                 // add 2 boom cores
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DualBoomAndRocketOneHwacha
 
 class DualLargeBoomAndDualRocketConfig extends Config(
-  new boom.common.WithNLargeBooms(2) ++                   // add 2 boom cores
+  new boom.v3.common.WithNLargeBooms(2) ++                   // add 2 boom cores
   new freechips.rocketchip.subsystem.WithNBigCores(2) ++  // add 2 rocket cores
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: DualBoomAndSingleRocket
 class DualLargeBoomAndSingleRocketConfig extends Config(
-  new boom.common.WithNLargeBooms(2) ++                   // add 2 boom cores
+  new boom.v3.common.WithNLargeBooms(2) ++                   // add 2 boom cores
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++  // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
@@ -58,7 +58,7 @@ class DualLargeBoomAndSingleRocketConfig extends Config(
 
 class LargeBoomAndRocketWithControlCoreConfig extends Config(
   new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small "control" core
-  new boom.common.WithNLargeBooms(1) ++                    // Add 1 boom core
+  new boom.v3.common.WithNLargeBooms(1) ++                    // Add 1 boom core
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala

@@ -50,10 +50,10 @@ class MempressRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
-class HwachaLargeBoomConfig extends Config(
+class HwachaLargeBoomV3Config extends Config(
   new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
-  new boom.common.WithNLargeBooms(1) ++
+  new boom.v3.common.WithNLargeBooms(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 

generators/chipyard/src/main/scala/config/TracegenConfigs.scala

@@ -32,8 +32,13 @@ class NonBlockingTraceGenConfig extends Config(
   new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
   new AbstractTraceGenConfig)
 
-class BoomTraceGenConfig extends Config(
+class BoomV3TraceGenConfig extends Config(
-  new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
+  new tracegen.WithBoomV3TraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new AbstractTraceGenConfig)
+
+class BoomV4TraceGenConfig extends Config(
+  new tracegen.WithBoomV4TraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
   new freechips.rocketchip.subsystem.WithInclusiveCache ++
   new AbstractTraceGenConfig)
 

generators/chipyard/src/main/scala/config/TutorialConfigs.scala

@@ -32,7 +32,7 @@ class TutorialStarterConfig extends Config(
   // Uncomment out one (or multiple) of the lines below, and choose
   // how many cores you want.
   // new freechips.rocketchip.subsystem.WithNBigCores(1) ++    // Specify we want some number of Rocket cores
-  // new boom.common.WithNSmallBooms(1) ++                     // Specify we want some number of BOOM cores
+  // new boom.v3.common.WithNSmallBooms(1) ++                     // Specify we want some number of BOOM cores
 
   // CUSTOMIZE the L2
   // Uncomment this line, and specify a size if you want to have a L2

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -7,7 +7,6 @@ import freechips.rocketchip.tile._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
 
-import boom.common.{BoomTileAttachParams}
 import cva6.{CVA6TileAttachParams}
 import sodor.common.{SodorTileAttachParams}
 import ibex.{IbexTileAttachParams}
@@ -18,7 +17,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
     case other => other
   }
@@ -26,7 +27,9 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
 
 class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(trace = true)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(trace = true)))
     case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
@@ -37,7 +40,9 @@ class WithTraceIO extends Config((site, here, up) => {
 
 class WithNoTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(trace = false)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(trace = false)))
     case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = false))
@@ -50,7 +55,9 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nPerfCounters = n)))
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nPerfCounters = n)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nPerfCounters = n)))
     case other => other
   }
@@ -60,7 +67,9 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nPMPs = n)))
-    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nPMPs = n)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       core = tp.tileParams.core.copy(nPMPs = n)))
     case other => other
   }
@@ -95,7 +104,9 @@ class WithTilePrefetchers extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
       master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
-    case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
+    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
+      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
+    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
       master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
     case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
       master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
@@ -108,10 +119,10 @@ class WithTilePrefetchers extends Config((site, here, up) => {
 
 // Adds boundary buffers to RocketTiles, which places buffers between the caches and the TileLink interface
 // This typically makes it easier to close timing
-class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {                                                                                                                                                           
+class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {                                                                                                                                                                                                                                                      
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
-    case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(                                                                                                                                                                                                                                                
+    case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(
-      boundaryBuffers=buffers                                                                                                                                                                                                                                                                                                
+      boundaryBuffers=buffers
-    ))                                                                                                                                                                                                                                                                                                                       
+    ))
-  }                                                                                                                                                                                                                                                                                                                          
+  }
-})   
+})

generators/firechip/src/main/scala/FireSim.scala

@@ -13,7 +13,7 @@ import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
 import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
 import freechips.rocketchip.tile.{RocketTile}
-import boom.common.{BoomTile}
+import boom.v3.common.{BoomTile}
 
 import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock, ResetPulseBridge, ResetPulseBridgeParameters}
 import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotation}
@@ -112,10 +112,10 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
           case b: BoomTile => {
             val core = b.module.core
             core.iregfile match {
-              case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+              case irf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
             }
             if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
-              case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
+              case frf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
             }
           }
           case _ =>

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -201,7 +201,7 @@ class WithFireSimTestChipConfigTweaks extends Config(
   new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
   new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
   new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
-  new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
+  new boom.v3.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
   new WithFireSimDesignTweaks
 )
 
@@ -273,13 +273,13 @@ class FireSimSmallSystemConfig extends Config(
   new chipyard.RocketConfig)
 
 //*****************************************************************
-// Boom config, base off chipyard's LargeBoomConfig
+// Boom config, base off chipyard's LargeBoomV3Config
 //*****************************************************************
 class FireSimLargeBoomConfig extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
-  new chipyard.LargeBoomConfig)
+  new chipyard.LargeBoomV3Config)
 
 //********************************************************************
 // Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
@@ -335,11 +335,11 @@ class FireSimCVA6Config extends Config(
 // - Requires MTModels and MCRams mixins as prefixes to the platform config
 // - May require larger build instances or JVM memory footprints
 //*********************************************************************************/
-class FireSim16LargeBoomConfig extends Config(
+class FireSim16LargeBoomV3Config extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
-  new boom.common.WithNLargeBooms(16) ++
+  new boom.v3.common.WithNLargeBooms(16) ++
   new chipyard.config.AbstractConfig)
 
 class FireSimNoMemPortConfig extends Config(
@@ -366,4 +366,4 @@ class FireSimLargeBoomCospikeConfig extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks++
-  new chipyard.LargeBoomConfig)
+  new chipyard.LargeBoomV3Config)

generators/tracegen/src/main/scala/Configs.scala

@@ -8,7 +8,6 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.BaseConfig
 import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
-import boom.lsu._
 import scala.math.{max, min}
 
 class WithTraceGen(
@@ -50,7 +49,7 @@ class WithTraceGen(
   case NumTiles => up(NumTiles) + n
 })
 
-class WithBoomTraceGen(
+class WithBoomV3TraceGen(
   n: Int = 2,
   overrideMemOffset: Option[BigInt] = None)(
   params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
@@ -61,8 +60,44 @@ class WithBoomTraceGen(
     val idOffset = up(NumTiles)
     val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
     params.zipWithIndex.map { case (dcp, i) =>
-      BoomTraceGenTileAttachParams(
+      boom.v3.lsu.BoomTraceGenTileAttachParams(
-        tileParams = BoomTraceGenParams(
+        tileParams = boom.v3.lsu.BoomTraceGenParams(
+          tileId = i + idOffset,
+          dcache = Some(dcp),
+          wordBits = site(XLen),
+          addrBits = 48,
+          addrBag = {
+            val nSets = dcp.nSets
+            val nWays = dcp.nWays
+            val blockOffset = site(SystemBusKey).blockOffset
+            val nBeats = site(SystemBusKey).blockBeats
+            List.tabulate(nWays) { i =>
+              Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
+            }.flatten
+          },
+          maxRequests = nReqs,
+          memStart = memOffset,
+          numGens = params.size),
+        crossingParams = RocketCrossingParams()
+      )
+    } ++ prev
+  }
+  case NumTiles => up(NumTiles) + n
+})
+
+class WithBoomV4TraceGen(
+  n: Int = 2,
+  overrideMemOffset: Option[BigInt] = None)(
+  params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
+  nReqs: Int = 8192
+) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => {
+    val prev = up(TilesLocated(InSubsystem), site)
+    val idOffset = up(NumTiles)
+    val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
+    params.zipWithIndex.map { case (dcp, i) =>
+      boom.v4.lsu.BoomTraceGenTileAttachParams(
+        tileParams = boom.v4.lsu.BoomTraceGenParams(
           tileId = i + idOffset,
           dcache = Some(dcp),
           wordBits = site(XLen),

generators/tracegen/src/main/scala/System.scala

@@ -6,7 +6,6 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
 import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar}
 import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
 import freechips.rocketchip.subsystem._
-import boom.lsu.BoomTraceGenTile
 
 class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
     with InstantiatesHierarchicalElements
@@ -20,7 +19,8 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
 
   val tileStatusNodes = totalTiles.values.toSeq.collect {
     case t: GroundTestTile => t.statusNode.makeSink()
-    case t: BoomTraceGenTile => t.statusNode.makeSink()
+    case t: boom.v3.lsu.BoomTraceGenTile => t.statusNode.makeSink()
+    case t: boom.v4.lsu.BoomTraceGenTile => t.statusNode.makeSink()
   }
 
   lazy val fakeClockDomain = sbus.generateSynchronousDomain