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Bump boom

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This commit is contained in:
Jerry Zhao
2024-03-06 21:54:29 -08:00
parent e041c3bae4
commit 4203d50bc2
18 changed files with 284 additions and 93 deletions
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6
generators/firechip/src/main/scala/FireSim.scala
View File

@@ -13,7 +13,7 @@ import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
import freechips.rocketchip.tile.{RocketTile}
import boom.common.{BoomTile}
import boom.v3.common.{BoomTile}
import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock, ResetPulseBridge, ResetPulseBridgeParameters}
import midas.targetutils.{MemModelAnnotation, EnableModelMultiThreadingAnnotation}
@@ -112,10 +112,10 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
case b: BoomTile => {
val core = b.module.core
core.iregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case irf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
}
if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
case frf: boom.v3.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
}
}
case _ =>

12
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -201,7 +201,7 @@ class WithFireSimTestChipConfigTweaks extends Config(
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new boom.v3.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
new WithFireSimDesignTweaks
)
@@ -273,13 +273,13 @@ class FireSimSmallSystemConfig extends Config(
new chipyard.RocketConfig)
//*****************************************************************
// Boom config, base off chipyard's LargeBoomConfig
// Boom config, base off chipyard's LargeBoomV3Config
//*****************************************************************
class FireSimLargeBoomConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.LargeBoomConfig)
new chipyard.LargeBoomV3Config)
//********************************************************************
// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
@@ -335,11 +335,11 @@ class FireSimCVA6Config extends Config(
// - Requires MTModels and MCRams mixins as prefixes to the platform config
// - May require larger build instances or JVM memory footprints
//*********************************************************************************/
class FireSim16LargeBoomConfig extends Config(
class FireSim16LargeBoomV3Config extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new boom.common.WithNLargeBooms(16) ++
new boom.v3.common.WithNLargeBooms(16) ++
new chipyard.config.AbstractConfig)
class FireSimNoMemPortConfig extends Config(
@@ -366,4 +366,4 @@ class FireSimLargeBoomCospikeConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks++
new chipyard.LargeBoomConfig)
new chipyard.LargeBoomV3Config)