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Merge pull request #1303 from ucb-bar/ultrabump

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Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip
This commit is contained in:
Jerry Zhao
2023-02-01 18:10:38 -08:00
committed by GitHub
parent 6fbdacbd8b f0df5a9d83
commit 41fd20a11e
35 changed files with 87 additions and 97 deletions
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6
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -76,7 +76,7 @@ class WithSerialBridge extends OverrideHarnessBinder({
val ram = withClockAndReset(th.buildtopClock, th.buildtopReset) {
SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
}
SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.buildtopReset.asBool)
}
Nil
}
@@ -97,7 +97,7 @@ class WithUARTBridge extends OverrideHarnessBinder({
val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode
val pbusClock = pbusClockNode.in.head._1.clock
BoringUtils.bore(pbusClock, Seq(uartSyncClock))
ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil
ports.map { p => UARTBridge(uartSyncClock, p, th.buildtopReset.asBool)(system.p) }; Nil
})
class WithBlockDeviceBridge extends OverrideHarnessBinder({
@@ -134,7 +134,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
axiClockBundle,
th.buildtopReset)
}
SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName))
SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool)
// connect SimAxiMem
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) =>