Bump firesim | fix testchipip segfaults

2024-01-01 15:44:23 -08:00
parent 5f2b2181c2
commit 41651edbdc
4 changed files with 5 additions and 5 deletions
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -100,7 +100,7 @@ class WithSimAXIMem extends HarnessBinder({
  case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => {
    val mem = LazyModule(new SimAXIMem(port.edge, size=port.params.master.size)(Parameters.empty))
    withClock(port.io.clock) { Module(mem.module) }
-    mem.io_axi4.head <> port.io
+    mem.io_axi4.head <> port.io.bits
  }
 })

--- a/generators/testchipip
+++ b/generators/testchipip