diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index a6e6791a..6406d6c6 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -61,9 +61,7 @@ class WithFASEDBridge extends RegisterBridgeBinder({
     }).toSeq
 })
 
-class WithTracerVBridge extends RegisterBridgeBinder({
-  case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p)
-})
+class WithTracerVBridge extends Config((_,_,_) => { case InstantiateTracerVBridges => true })
 
 class WithTraceGenBridge extends RegisterBridgeBinder({
   case target: HasTraceGenTilesModuleImp =>
diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala
index 6320038a..50d51269 100644
--- a/generators/firechip/src/main/scala/TargetMixins.scala
+++ b/generators/firechip/src/main/scala/TargetMixins.scala
@@ -12,7 +12,7 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.tile.RocketTile
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.TracedInstruction
-import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction}
+import firesim.bridges.{TracerVBridge}
 import firesim.util.{HasAdditionalClocks, FireSimClockKey}
 
 import midas.targetutils.MemModelAnnotation
@@ -22,34 +22,33 @@ import boom.common.BoomTile
 /* Wires out tile trace ports to the top; and wraps them in a Bundle that the
  * TracerV bridge can match on.
  */
-object PrintTracePort extends Field[Boolean](false)
+case object PrintTracePort extends Field[Boolean](false)
+case object InstantiateTracerVBridges extends Field[Boolean](false)
 
 trait HasTraceIO {
   this: HasTiles =>
   val module: HasTraceIOImp
 
   // Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp
-  val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]]
-  val tileTraceNodes = tiles.map(tile => tile.traceNode)
-  tileTraceNodes foreach { traceNexus := _ }
+  val tileTraceNodes = tiles.map({ tile =>
+    val node = BundleBridgeSink[Vec[TracedInstruction]]
+    node := tile.traceNode
+    node
+  })
 }
 
 trait HasTraceIOImp extends LazyModuleImp {
   val outer: HasTraceIO
-
-  val traceIO = IO(Output(new TraceOutputTop(
-    DeclockedTracedInstruction.fromNode(outer.traceNexus.in))))
-  (traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) =>
-    port := DeclockedTracedInstruction.fromVec(tileTrace)
+  outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) =>
+    if (p(InstantiateTracerVBridges)) {
+      val b = TracerVBridge(node.bundle)
+      if (p(PrintTracePort)) {
+        val traceprint = WireDefault(0.U(512.W))
+        traceprint := b.io.traces.asUInt
+        printf(s"TRACEPORT ${idx}: %x\n", traceprint)
+      }
+    }
   })
-  traceIO.clock := clock
-
-  // Enabled to test TracerV trace capture
-  if (p(PrintTracePort)) {
-    val traceprint = Wire(UInt(512.W))
-    traceprint := Cat(traceIO.traces.map(_.asUInt))
-    printf("TRACEPORT: %x\n", traceprint)
-  }
 }
 
 trait CanHaveMultiCycleRegfileImp {
diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala
index a2f39523..7f505ab1 100644
--- a/generators/firechip/src/test/scala/ScalaTestSuite.scala
+++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala
@@ -106,14 +106,17 @@ abstract class FireSimTestSuite(
   def diffTracelog(verilatedLog: String) {
     behavior of "captured instruction trace"
     it should s"match the chisel printf in ${verilatedLog}" in {
-      def getLines(file: File, dropLines: Int = 0): Seq[String] = {
+      def getLines(file: File, dropLines: Int = 0, prefixFilter: String = ""): Seq[String] = {
         val lines = Source.fromFile(file).getLines.toList
-        lines.filter(_.startsWith("TRACEPORT")).drop(dropLines)
+        lines.filter(_.startsWith(prefixFilter))
+             .drop(dropLines)
+             .map(_.stripPrefix(prefixFilter))
       }
       val resetLength = 51
-      val verilatedOutput  = getLines(new File(outDir,  s"/${verilatedLog}"))
-      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength)
-      assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, "Outputs differ in length")
+      val verilatedOutput  = getLines(new File(outDir,  s"/${verilatedLog}"), prefixFilter = "TRACEPORT 0: ")
+      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), dropLines = resetLength)
+      assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1,
+        s"\nPrintf Length: ${verilatedOutput.size}, Trace Length: ${synthPrintOutput.size}")
       assert(verilatedOutput.nonEmpty)
       for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) {
         assert(vPrint == sPrint)
@@ -125,7 +128,7 @@ abstract class FireSimTestSuite(
   mkdirs
   elaborate
   generateTestSuiteMakefrags
-  runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0"""))
+  runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
   diffTracelog("rv64ui-p-simple.out")
   runSuite("verilator")(benchmarks)
   runSuite("verilator")(FastBlockdevTests)