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Support breaking out ChipTop I/O out of the expected bundle type

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This commit is contained in:
Jerry Zhao
2023-10-30 21:25:11 -07:00
parent a5597fd32f
commit 3fa3d745b9
12 changed files with 101 additions and 77 deletions
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52
generators/chipyard/src/main/scala/iobinders/Ports.scala
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@@ -16,7 +16,9 @@ import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}
trait Port[T <: Data] {
val io: T
val getIO: () => T
// port.io should only be called in the TestHarness context
lazy val io = getIO()
}
trait HasChipyardPorts {
@@ -24,75 +26,75 @@ trait HasChipyardPorts {
}
// These case classes are generated by IOBinders, and interpreted by HarnessBinders
case class GPIOPort (val io: Analog, val gpioId: Int, val pinId: Int)
case class GPIOPort (val getIO: () => Analog, val gpioId: Int, val pinId: Int)
extends Port[Analog]
case class GPIOPinsPort (val io: GPIOPortIO, val gpioId: Int)
case class GPIOPinsPort (val getIO: () => GPIOPortIO, val gpioId: Int)
extends Port[GPIOPortIO]
case class I2CPort (val io: sifive.blocks.devices.i2c.I2CPort)
case class I2CPort (val getIO: () => sifive.blocks.devices.i2c.I2CPort)
extends Port[sifive.blocks.devices.i2c.I2CPort]
case class UARTPort (val io: UARTPortIO, val uartNo: Int, val freqMHz: Int)
case class UARTPort (val getIO: () => UARTPortIO, val uartNo: Int, val freqMHz: Int)
extends Port[UARTPortIO]
case class SPIFlashPort (val io: SPIChipIO, val params: SPIFlashParams, val spiId: Int)
case class SPIFlashPort (val getIO: () => SPIChipIO, val params: SPIFlashParams, val spiId: Int)
extends Port[SPIChipIO]
case class SPIPort (val io: SPIPortIO)
case class SPIPort (val getIO: () => SPIPortIO)
extends Port[SPIPortIO]
case class BlockDevicePort (val io: ClockedIO[BlockDeviceIO], val params: BlockDeviceConfig)
case class BlockDevicePort (val getIO: () => ClockedIO[BlockDeviceIO], val params: BlockDeviceConfig)
extends Port[ClockedIO[BlockDeviceIO]]
case class NICPort (val io: ClockedIO[NICIOvonly], val params: NICConfig)
case class NICPort (val getIO: () => ClockedIO[NICIOvonly], val params: NICConfig)
extends Port[ClockedIO[NICIOvonly]]
case class AXI4MemPort (val io: ClockedIO[AXI4Bundle], val params: MemoryPortParams, val edge: AXI4EdgeParameters, val clockFreqMHz: Int)
case class AXI4MemPort (val getIO: () => ClockedIO[AXI4Bundle], val params: MemoryPortParams, val edge: AXI4EdgeParameters, val clockFreqMHz: Int)
extends Port[ClockedIO[AXI4Bundle]]
case class AXI4MMIOPort (val io: ClockedIO[AXI4Bundle], val params: MasterPortParams, val edge: AXI4EdgeParameters)
case class AXI4MMIOPort (val getIO: () => ClockedIO[AXI4Bundle], val params: MasterPortParams, val edge: AXI4EdgeParameters)
extends Port[ClockedIO[AXI4Bundle]]
case class AXI4InPort (val io: ClockedIO[AXI4Bundle], val params: SlavePortParams)
case class AXI4InPort (val getIO: () => ClockedIO[AXI4Bundle], val params: SlavePortParams)
extends Port[ClockedIO[AXI4Bundle]]
case class ExtIntPort (val io: UInt)
case class ExtIntPort (val getIO: () => UInt)
extends Port[UInt]
case class DMIPort (val io: ClockedDMIIO)
case class DMIPort (val getIO: () => ClockedDMIIO)
extends Port[ClockedDMIIO]
case class JTAGPort (val io: JTAGChipIO)
case class JTAGPort (val getIO: () => JTAGChipIO)
extends Port[JTAGChipIO]
case class SerialTLPort (val io: ClockedIO[SerialIO], val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int)
case class SerialTLPort (val getIO: () => ClockedIO[SerialIO], val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int)
extends Port[ClockedIO[SerialIO]]
case class UARTTSIPort (val io: UARTTSIIO)
case class UARTTSIPort (val getIO: () => UARTTSIIO)
extends Port[UARTTSIIO]
case class SuccessPort (val io: Bool)
case class SuccessPort (val getIO: () => Bool)
extends Port[Bool]
case class TracePort (val io: TraceOutputTop, val cosimCfg: SpikeCosimConfig)
case class TracePort (val getIO: () => TraceOutputTop, val cosimCfg: SpikeCosimConfig)
extends Port[TraceOutputTop]
case class CustomBootPort (val io: Bool)
case class CustomBootPort (val getIO: () => Bool)
extends Port[Bool]
case class ClockPort (val io: Clock, val freqMHz: Double)
case class ClockPort (val getIO: () => Clock, val freqMHz: Double)
extends Port[Clock]
case class ResetPort (val io: AsyncReset)
case class ResetPort (val getIO: () => AsyncReset)
extends Port[Reset]
case class DebugResetPort (val io: Reset)
case class DebugResetPort (val getIO: () => Reset)
extends Port[Reset]
case class JTAGResetPort (val io: Reset)
case class JTAGResetPort (val getIO: () => Reset)
extends Port[Reset]
case class TLMemPort (val io: HeterogeneousBag[TLBundle])
case class TLMemPort (val getIO: () => HeterogeneousBag[TLBundle])
extends Port[HeterogeneousBag[TLBundle]]