Support breaking out ChipTop I/O out of the expected bundle type

2023-10-30 21:25:11 -07:00
parent a5597fd32f
commit 3fa3d745b9
12 changed files with 101 additions and 77 deletions
--- a/fpga/src/main/scala/arty/IOBinders.scala
+++ b/fpga/src/main/scala/arty/IOBinders.scala
@@ -18,6 +18,6 @@ class WithDebugResetPassthrough extends ComposeIOBinder({
    val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
    sjtag.reset := io_sjtag_reset

-    (Seq(DebugResetPort(io_ndreset), JTAGResetPort(io_sjtag_reset)), Nil)
+    (Seq(DebugResetPort(() => io_ndreset), JTAGResetPort(() => io_sjtag_reset)), Nil)
  }
 })