BOOM Bump w. Fromajo (#523)
* [uart] add uart adapter | add uart + adapter to all configs * [uart] change pty define name | add uart to all configs that need it * [uart] default to 115200 baudrate * [dromajo] first working commit * [dromajo] bump boom for commit-width > 1 fix * [dromajo] adjust dromajo commits * [dromajo] bump boom * commit dromajo changes * extra * [dromajo] add block device to configs * rebump older modules * bump firesim * [chipyard] enable dromajo in midas level simulation * [testchipip] forgot to bump * get rid of breaking things * bump firesim * bump boom * Bump BOOM to ifu3 WIP * bump firesim * fix how memory is passed to dromajo * bump boom and firesim * fix merge issues * add dromajo cosim bridge in chipyard * move traceio back into testchipip (#488) * refer to testchipip traceio in firechip (#490) * Move TraceIO fragment to chipyard (#492) * fix chipyard dromajo bridge (#493) * Sboom dromajo bump (#501) * [FireChip] Use clock in BridgeBinders * [firesim] Update TraceGen BridgeBinder * [Firechip] Add support for Tile <-> Uncore rational division * [firesim] Update the multiclock test * [firechip] Commit some Eagle X-related mock configs * [firechip] Instantiate multiple TracerV bridges * [Firechip] Include reset in tracerv tokens * [TracerV] Drop the first token in comparison tests * [Firechip] Make reverse instruction order in trace printf * WARNING: Point at a fork of boom @ davidbiancolin * [firesim] Update ClockBridge API * Add Gemmini to README [ci skip] (#487) * [firechip] Isolate all firesim-multiclock stuff in a single file * add documentation on ring network and system bus * Bump firesim for CI * Bump FireSim * Bump testchipip to dev [ci skip] * Bump FireSim * [make] split up specific make vars/targets into frags (#499) * [make] split up specific make vars/targets into frags * [make] move dramsim and max-cycles into SIM_FLAGS * [misc] move ariane configs to configs/ folder * [dromajo] add dromajo * [dromajo] bump for new traceio changes * bump firesim * bump firesim * point to chipyard traceio * bump boom Co-authored-by: David Biancolin <david.biancolin@gmail.com> Co-authored-by: Howard Mao <zhehao.mao@gmail.com> * Support Dromajo + TracerV configurations * [docs] add documentation for Dromajo in FireSim + Chipyard * add a bit more docs * [docs] bump docs * [firesim] dump artefacts in firesim * [firesim] update firesim * [testchipip] remove extraneous items in testchipip * [dromajo] prevent dromajo from breaking when params unset * update firesim, dromajo, and testchipip * [firesim] bump firesim * [firesim] bump firesim * [misc] bump firesim and testchipip for reviewer comments * remove WithNoGPIO fragment * bump firesim * bump dromajo boom config * bump firesim * generate artefacts in firesim testsuite Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com> Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu> Co-authored-by: David Biancolin <david.biancolin@gmail.com> Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
This commit is contained in:
Jerry Zhao
@@ -13,7 +13,7 @@ import freechips.rocketchip.tile.{RocketTile}
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import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
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import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
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import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp}
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import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
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import icenet.CanHavePeripheryIceNICModuleImp
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import junctions.{NastiKey, NastiParameters}
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@@ -27,7 +27,8 @@ import ariane.ArianeTile
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import boom.common.{BoomTile}
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import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
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import chipyard.HasChipyardTilesModuleImp
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import chipyard.{HasChipyardTilesModuleImp}
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import testchipip.{CanHaveTraceIOModuleImp}
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object MainMemoryConsts {
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val regionNamePrefix = "MainMemory"
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@@ -72,12 +73,20 @@ class WithFASEDBridge extends OverrideIOBinder({
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}
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})
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class WithTracerVBridge extends OverrideIOBinder({
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class WithTracerVBridge extends ComposeIOBinder({
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(system: CanHaveTraceIOModuleImp) =>
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system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil
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})
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class WithDromajoBridge extends ComposeIOBinder({
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(system: CanHaveTraceIOModuleImp) => {
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system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil
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}
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})
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class WithTraceGenBridge extends OverrideIOBinder({
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(system: HasTraceGenTilesModuleImp) =>
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GroundTestBridge(system.clock, system.success)(system.p); Nil
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@@ -116,7 +125,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({
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(system: HasPeripheryDebugModuleImp) => {
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Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
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// tieoffDebug doesn't actually tie everything off :/
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system.debug.foreach { d =>
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system.debug.foreach { d =>
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d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
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d.dmactiveAck := DontCare
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}
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@@ -45,6 +45,7 @@ class FireSim(implicit val p: Parameters) extends RawModule {
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}))
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(lazyModule, Module(lazyModule.module))
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}
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val peekPokeBridge = PeekPokeBridge(clock, reset)
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// A Seq of partial functions that will instantiate the right bridge only
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// if that Mixin trait is present in the target's LazyModule class instance
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@@ -79,6 +79,7 @@ class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop
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override lazy val module = new FiresimMulticlockTopModule(this)
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}
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class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp
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// Harness Definition
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@@ -73,13 +73,6 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
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// Enables tracing on all cores
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class WithTraceIO extends Config((site, here, up) => {
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case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
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case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
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case TracePortKey => Some(TracePortParams())
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})
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// Tweaks that are generally applied to all firesim configs
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class WithFireSimConfigTweaks extends Config(
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@@ -92,7 +85,7 @@ class WithFireSimConfigTweaks extends Config(
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// Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
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new WithoutTLMonitors ++
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// Optional: Adds IO to attach tracerV bridges
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new WithTraceIO ++
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new chipyard.config.WithTraceIO ++
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// Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
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new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
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// Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
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@@ -143,7 +136,6 @@ class FireSimLargeBoomConfig extends Config(
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new WithFireSimConfigTweaks ++
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new chipyard.LargeBoomConfig)
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//********************************************************************
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// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
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//********************************************************************
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@@ -75,7 +75,7 @@ abstract class FireSimTestSuite(
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case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv"
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case _ => ""
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}
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val results = suite.names.toSeq sliding (N, N) map { t =>
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val results = suite.names.toSeq sliding (N, N) map { t =>
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val subresults = t map (name =>
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Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
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Await result (Future sequence subresults, Duration.Inf)
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@@ -130,6 +130,7 @@ abstract class FireSimTestSuite(
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mkdirs
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elaborate
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generateTestSuiteMakefrags
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generateArtefacts
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runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
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//diffTracelog("rv64ui-p-simple.out")
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runSuite("verilator")(benchmarks)
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