BOOM Bump w. Fromajo (#523)

* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -13,7 +13,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
 import freechips.rocketchip.util.{AsyncResetReg}
 
 import boom.common.{BoomTilesKey}
-
+import ariane.{ArianeTilesKey}
 import testchipip._
 
 import hwacha.{Hwacha}
@@ -153,3 +153,9 @@ class WithControlCore extends Config((site, here, up) => {
     )
   case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
 })
+
+class WithTraceIO extends Config((site, here, up) => {
+  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
+  case TracePortKey => Some(TracePortParams())
+})

generators/chipyard/src/main/scala/IOBinders.scala

@@ -351,4 +351,12 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({
   }
 })
 
+class WithSimDromajoBridge extends ComposeIOBinder({
+   (system: CanHaveTraceIOModuleImp) => {
+     system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) }
+     Nil
+   }
+})
+
+
 } /* end package object */

generators/chipyard/src/main/scala/Subsystem.scala

@@ -104,4 +104,29 @@ class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModule
 
   // create file with boom params
   ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
+
+  // Generate C header with relevant information for Dromajo
+  // THIS IS INCLUDED IN THE `dromajo_params.h` header file
+  var dromajoParams: String = ""
+  dromajoParams += "#ifndef DROMAJO_PARAMS_H"
+  dromajoParams += "\n#define DROMAJO_PARAMS_H"
+  dromajoParams += "\n\n" + "#define DROMAJO_RESET_VECTOR " + "\"" + "0x" + f"${p(BootROMParams).hang}%X" + "\""
+  dromajoParams += "\n" + "#define DROMAJO_MMIO_START " + "\"" + "0x" + f"${p(BootROMParams).address + p(BootROMParams).size}%X" + "\""
+  p(ExtMem) map { eP =>
+    dromajoParams += "\n" + "#define DROMAJO_MMIO_END " + "\"" + "0x" + f"${eP.master.base}%X" + "\""
+    // dromajo memory is in MiB chunks
+    dromajoParams += "\n" + "#define DROMAJO_MEM_SIZE " + "\"" + "0x" + f"${eP.master.size >> 20}%X" + "\""
+  }
+  p(PLICKey) map { pP =>
+    dromajoParams += "\n" + "#define DROMAJO_PLIC_BASE " + "\"" + "0x" + f"${pP.baseAddress}%X" + "\""
+    dromajoParams += "\n" + "#define DROMAJO_PLIC_SIZE " + "\"" + "0x" + f"${PLICConsts.size(pP.maxHarts)}%X" + "\""
+  }
+  p(CLINTKey) map { cP =>
+    dromajoParams += "\n" + "#define DROMAJO_CLINT_BASE " + "\"" + "0x" + f"${cP.baseAddress}%X" + "\""
+    dromajoParams += "\n" + "#define DROMAJO_CLINT_SIZE " + "\"" + "0x" + f"${CLINTConsts.size}%X" + "\""
+  }
+  dromajoParams += "\n\n#endif"
+
+  ElaborationArtefacts.add("""dromajo_params.h""", dromajoParams)
+
 }

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -163,3 +163,24 @@ class LoopbackNICLargeBoomConfig extends Config(
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
   new freechips.rocketchip.system.BaseConfig)
 
+class DromajoBoomConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.iobinders.WithSimDromajoBridge ++                 // attach Dromajo
+  new testchipip.WithTSI ++
+  new chipyard.config.WithTraceIO ++                             // enable the traceio
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithUART ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new boom.common.WithSmallBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)
+

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -13,7 +13,7 @@ import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
 
-import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp}
+import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
 import icenet.CanHavePeripheryIceNICModuleImp
 
 import junctions.{NastiKey, NastiParameters}
@@ -27,7 +27,8 @@ import ariane.ArianeTile
 import boom.common.{BoomTile}
 
 import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
-import chipyard.HasChipyardTilesModuleImp
+import chipyard.{HasChipyardTilesModuleImp}
+import testchipip.{CanHaveTraceIOModuleImp}
 
 object MainMemoryConsts {
   val regionNamePrefix = "MainMemory"
@@ -72,12 +73,20 @@ class WithFASEDBridge extends OverrideIOBinder({
   }
 })
 
-class WithTracerVBridge extends OverrideIOBinder({
+class WithTracerVBridge extends ComposeIOBinder({
   (system: CanHaveTraceIOModuleImp) =>
     system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil
 })
 
 
+
+class WithDromajoBridge extends ComposeIOBinder({
+  (system: CanHaveTraceIOModuleImp) => {
+    system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil
+  }
+})
+
+
 class WithTraceGenBridge extends OverrideIOBinder({
   (system: HasTraceGenTilesModuleImp) =>
     GroundTestBridge(system.clock, system.success)(system.p); Nil
@@ -116,7 +125,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({
   (system: HasPeripheryDebugModuleImp) => {
     Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
     // tieoffDebug doesn't actually tie everything off :/
-    system.debug.foreach { d => 
+    system.debug.foreach { d =>
       d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
       d.dmactiveAck := DontCare
     }

generators/firechip/src/main/scala/FireSim.scala

@@ -45,6 +45,7 @@ class FireSim(implicit val p: Parameters) extends RawModule {
       }))
       (lazyModule, Module(lazyModule.module))
     }
+
     val peekPokeBridge = PeekPokeBridge(clock, reset)
     // A Seq of partial functions that will instantiate the right bridge only
     // if that Mixin trait is present in the target's LazyModule class instance

generators/firechip/src/main/scala/FireSimMulticlockPOC.scala

@@ -79,6 +79,7 @@ class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop
   override lazy val module = new FiresimMulticlockTopModule(this)
 }
 
+
 class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp
 
 // Harness Definition

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -73,13 +73,6 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
 
 
 
-// Enables tracing on all cores
-class WithTraceIO extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
-  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
-  case TracePortKey => Some(TracePortParams())
-})
-
 
 // Tweaks that are generally applied to all firesim configs
 class WithFireSimConfigTweaks extends Config(
@@ -92,7 +85,7 @@ class WithFireSimConfigTweaks extends Config(
   // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix)
   new WithoutTLMonitors ++
   // Optional: Adds IO to attach tracerV bridges
-  new WithTraceIO ++
+  new chipyard.config.WithTraceIO ++
   // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
   new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
   // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
@@ -143,7 +136,6 @@ class FireSimLargeBoomConfig extends Config(
   new WithFireSimConfigTweaks ++
   new chipyard.LargeBoomConfig)
 
-
 //********************************************************************
 // Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
 //********************************************************************

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -75,7 +75,7 @@ abstract class FireSimTestSuite(
         case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv"
         case _ => ""
       }
-      val results = suite.names.toSeq sliding (N, N) map { t => 
+      val results = suite.names.toSeq sliding (N, N) map { t =>
         val subresults = t map (name =>
           Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
         Await result (Future sequence subresults, Duration.Inf)
@@ -130,6 +130,7 @@ abstract class FireSimTestSuite(
   mkdirs
   elaborate
   generateTestSuiteMakefrags
+  generateArtefacts
   runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
   //diffTracelog("rv64ui-p-simple.out")
   runSuite("verilator")(benchmarks)

generators/tracegen/src/main/scala/Tile.scala

@@ -86,7 +86,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
 
   io.lsu.dis_uops(0).valid         := io.tracegen.req.fire()
   io.lsu.dis_uops(0).bits          := tracegen_uop
-  
+
   when (io.tracegen.req.fire()) {
     rob_tail := WrapInc(rob_tail, rob_sz)
     rob_bsy(rob_tail)   := true.B
@@ -165,8 +165,15 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
   io.lsu.rob_pnr_idx := rob_tail
   io.lsu.commit_load_at_rob_head := false.B
 
-  io.lsu.brinfo := DontCare
-  io.lsu.brinfo.valid := false.B
+  io.lsu.brupdate.b1 := (0.U).asTypeOf(new boom.exu.BrUpdateMasks)
+  io.lsu.brupdate.b2.uop := DontCare
+  io.lsu.brupdate.b2.mispredict := false.B
+  io.lsu.brupdate.b2.taken := false.B
+  io.lsu.brupdate.b2.cfi_type := 0.U
+  io.lsu.brupdate.b2.pc_sel := 0.U
+  io.lsu.brupdate.b2.jalr_target := 0.U
+  io.lsu.brupdate.b2.target_offset := 0.S(2.W)
+
   io.lsu.rob_head_idx := rob_head