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Fix clock group combiner behavior for rational-tile clocks

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This commit is contained in:
Jerry Zhao
2023-05-26 17:50:55 -07:00
parent f73951ac7f
commit 3f06dbc280
7 changed files with 10 additions and 9 deletions
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generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -171,6 +171,7 @@ class WithFireSimTestChipConfigTweaks extends Config(
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency
new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
// Crossing specifications
new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS