diff --git a/verisim/Makefile b/verisim/Makefile
index 466d616a..0379dc04 100644
--- a/verisim/Makefile
+++ b/verisim/Makefile
@@ -59,3 +59,6 @@ $(model_mk_debug): $(sim_vsrcs) $(INSTALLED_VERILATOR)
 
 $(sim_debug): $(model_mk_debug) $(sim_csrcs)
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
+
+clean:
+	rm -rf generated-src
diff --git a/vsim/Makefile b/vsim/Makefile
index 9d5d6d85..1fd8cb66 100644
--- a/vsim/Makefile
+++ b/vsim/Makefile
@@ -57,6 +57,6 @@ $(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
 	+define+DEBUG -debug_pp
 
 clean:
-	rm -rf csrc simv-* ucli.key vc_hdrs.h
+	rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h
 
 .PHONY: clean