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Rename fpga_platforms to chipyard_fpga

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This commit is contained in:
Jerry Zhao
2024-05-16 09:53:48 -07:00
parent 0c3ede15af
commit 3cf3d815dc
3 changed files with 7 additions and 7 deletions
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2
build.sbt
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@@ -324,6 +324,6 @@ lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
.settings(libraryDependencies ++= rocketLibDeps.value) .settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings) .settings(commonSettings)
lazy val fpga_platforms = (project in file("./fpga")) lazy val chipyard_fpga = (project in file("./fpga"))
.dependsOn(chipyard, fpga_shells) .dependsOn(chipyard, fpga_shells)
.settings(commonSettings) .settings(commonSettings)

2
docs/Prototyping/General.rst
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@@ -30,7 +30,7 @@ For example:
# converts to # converts to
make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream make SBT_PROJECT=chipyard_fpga MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream
Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``.
These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system.

10
fpga/Makefile
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@@ -17,7 +17,7 @@ sim_name := none
SUB_PROJECT ?= vcu118 SUB_PROJECT ?= vcu118
ifeq ($(SUB_PROJECT),vc707) ifeq ($(SUB_PROJECT),vc707)
SBT_PROJECT ?= fpga_platforms SBT_PROJECT ?= chipyard_fpga
MODEL ?= VC707FPGATestHarness MODEL ?= VC707FPGATestHarness
VLOG_MODEL ?= VC707FPGATestHarness VLOG_MODEL ?= VC707FPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.vc707 MODEL_PACKAGE ?= chipyard.fpga.vc707
@@ -31,7 +31,7 @@ ifeq ($(SUB_PROJECT),vc707)
endif endif
ifeq ($(SUB_PROJECT),vcu118) ifeq ($(SUB_PROJECT),vcu118)
SBT_PROJECT ?= fpga_platforms SBT_PROJECT ?= chipyard_fpga
MODEL ?= VCU118FPGATestHarness MODEL ?= VCU118FPGATestHarness
VLOG_MODEL ?= VCU118FPGATestHarness VLOG_MODEL ?= VCU118FPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.vcu118 MODEL_PACKAGE ?= chipyard.fpga.vcu118
@@ -45,7 +45,7 @@ ifeq ($(SUB_PROJECT),vcu118)
endif endif
ifeq ($(SUB_PROJECT),nexysvideo) ifeq ($(SUB_PROJECT),nexysvideo)
SBT_PROJECT ?= fpga_platforms SBT_PROJECT ?= chipyard_fpga
MODEL ?= NexysVideoHarness MODEL ?= NexysVideoHarness
VLOG_MODEL ?= NexysVideoHarness VLOG_MODEL ?= NexysVideoHarness
MODEL_PACKAGE ?= chipyard.fpga.nexysvideo MODEL_PACKAGE ?= chipyard.fpga.nexysvideo
@@ -60,7 +60,7 @@ endif
ifeq ($(SUB_PROJECT),arty35t) ifeq ($(SUB_PROJECT),arty35t)
# TODO: Fix with Arty # TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms SBT_PROJECT ?= chipyard_fpga
MODEL ?= Arty35THarness MODEL ?= Arty35THarness
VLOG_MODEL ?= Arty35THarness VLOG_MODEL ?= Arty35THarness
MODEL_PACKAGE ?= chipyard.fpga.arty MODEL_PACKAGE ?= chipyard.fpga.arty
@@ -74,7 +74,7 @@ ifeq ($(SUB_PROJECT),arty35t)
endif endif
ifeq ($(SUB_PROJECT),arty100t) ifeq ($(SUB_PROJECT),arty100t)
# TODO: Fix with Arty # TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms SBT_PROJECT ?= chipyard_fpga
MODEL ?= Arty100THarness MODEL ?= Arty100THarness
VLOG_MODEL ?= Arty100THarness VLOG_MODEL ?= Arty100THarness
MODEL_PACKAGE ?= chipyard.fpga.arty100t MODEL_PACKAGE ?= chipyard.fpga.arty100t