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Merge pull request #1208 from michael-etzkorn/main

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Update SiFive submodules to CHIPS fork
This commit is contained in:
Abraham Gonzalez
2022-09-01 10:54:56 -07:00
committed by GitHub
parent d5a18101e4 e5052022df
commit 3cd952bd32
2 changed files with 4 additions and 4 deletions
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2
.github/scripts/check-commit.sh vendored
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@@ -101,7 +101,7 @@ search
submodules=("fpga-shells") submodules=("fpga-shells")
dir="fpga" dir="fpga"
branches=("master") branches=("main")
search search
# turn off verbose printing to make this easier to read # turn off verbose printing to make this easier to read

6
.gitmodules vendored
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@@ -15,7 +15,7 @@
url = https://github.com/riscv-boom/riscv-boom.git url = https://github.com/riscv-boom/riscv-boom.git
[submodule "generators/sifive-blocks"] [submodule "generators/sifive-blocks"]
path = generators/sifive-blocks path = generators/sifive-blocks
url = https://github.com/sifive/sifive-blocks.git url = https://github.com/chipsalliance/rocket-chip-blocks.git
[submodule "generators/hwacha"] [submodule "generators/hwacha"]
path = generators/hwacha path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git url = https://github.com/ucb-bar/hwacha.git
@@ -27,7 +27,7 @@
url = https://github.com/firesim/icenet.git url = https://github.com/firesim/icenet.git
[submodule "generators/block-inclusivecache-sifive"] [submodule "generators/block-inclusivecache-sifive"]
path = generators/sifive-cache path = generators/sifive-cache
url = https://github.com/sifive/block-inclusivecache-sifive.git url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] [submodule "toolchains/riscv-tools/riscv-gnu-toolchain"]
path = toolchains/riscv-tools/riscv-gnu-toolchain path = toolchains/riscv-tools/riscv-gnu-toolchain
url = https://github.com/riscv/riscv-gnu-toolchain.git url = https://github.com/riscv/riscv-gnu-toolchain.git
@@ -121,7 +121,7 @@
url = https://github.com/ucb-bar/riscv-sodor.git url = https://github.com/ucb-bar/riscv-sodor.git
[submodule "fpga/fpga-shells"] [submodule "fpga/fpga-shells"]
path = fpga/fpga-shells path = fpga/fpga-shells
url = https://github.com/sifive/fpga-shells.git url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
[submodule "tools/api-config-chipsalliance"] [submodule "tools/api-config-chipsalliance"]
path = tools/api-config-chipsalliance path = tools/api-config-chipsalliance
url = https://github.com/chipsalliance/api-config-chipsalliance.git url = https://github.com/chipsalliance/api-config-chipsalliance.git