From 3cbcf6b6e82846274248ad6a52b50f43c0b15644 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 11 Oct 2023 15:01:39 -0700 Subject: [PATCH] Fix TSIBridge loadmem param --- generators/firechip/src/main/scala/BridgeBinders.scala | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 7982a75d..e4169ec2 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -72,8 +72,13 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({ val ram = LazyModule(new SerialRAM(port.serdesser)(Parameters.empty)) Module(ram.module) ram.module.io.ser <> port.io.bits - TSIBridge(th.harnessBinderClock, ram.module.io.tsi, - port.params.serialTLManagerParams.map(_ => MainMemoryConsts.globalName(th.p(MultiChipIdx))), th.harnessBinderReset.asBool)(th.p) + + // This assumes that: + // If ExtMem for the target is defined, then FASED bridge will be attached + // If FASED bridge is attached, loadmem widget is present + val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined + val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx))) + TSIBridge(th.harnessBinderClock, ram.module.io.tsi, mainMemoryName, th.harnessBinderReset.asBool)(th.p) } })