From 10ce4ee91aea1083cca2bd45c6f574170b96e1d5 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 19 Jun 2023 05:00:25 -0700 Subject: [PATCH 1/7] Revert "Revert "Merge pull request #1511 from ucb-bar/improve-peripheral"" This reverts commit cb24cf895585f168ef9b3b4cde793130014f2c84. --- .gitignore | 1 + .../fragments/PeripheralFragments.scala | 109 +++++++++++++++--- 2 files changed, 91 insertions(+), 19 deletions(-) diff --git a/.gitignore b/.gitignore index ac8e84d0..5dd75bec 100644 --- a/.gitignore +++ b/.gitignore @@ -27,3 +27,4 @@ project/project/ .ivy2 .sbt .classpath_cache/ +.vscode/ diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 3b607ae0..290e3dfe 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -6,7 +6,8 @@ import chisel3.util.{log2Up} import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey} -import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI} +import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig} +import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.stage.phases.TargetDirKey import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen} @@ -14,49 +15,119 @@ import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ +import sifive.blocks.devices.i2c._ import testchipip._ import chipyard.{ExtTLMem} -// Set the bootrom to the Chipyard bootrom -class WithBootROM extends Config((site, here, up) => { +/** + * Config fragment for adding a BootROM to the SoC + * + * @param address the address of the BootROM device + * @param size the size of the BootROM + * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset + * @param contentFileName the path to the BootROM image + */ +class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site) - .map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) + .map(_.copy( + address = address, + size = size, + hang = hang, + contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img" + )) }) -// DOC include start: gpio config fragment -class WithGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => Seq( - GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) -}) -// DOC include end: gpio config fragment - -class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => { - case PeripheryUARTKey => Seq( - UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) +/** + * Config fragment for adding a GPIO peripheral device to the SoC + * + * @param address the address of the GPIO device + * @param width the number of pins of the GPIO device + */ +class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((site, here, up) => { + case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( + GPIOParams(address = address, width = width, includeIOF = false)) }) +/** + * Config fragment for removing all UART peripheral devices from the SoC + */ class WithNoUART extends Config((site, here, up) => { case PeripheryUARTKey => Nil }) +/** + * Config fragment for adding a UART peripheral device to the SoC + * + * @param address the address of the UART device + * @param baudrate the baudrate of the UART device + */ +class WithUART(address: BigInt = 0x10020000, baudrate: BigInt = 115200) extends Config ((site, here, up) => { + case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq( + UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) +}) + class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries)) }) -class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { +/** + * Config fragment for adding a SPI peripheral device with Execute-in-Place capability to the SoC + * + * @param address the address of the SPI controller + * @param fAddress the address of the Execute-in-Place (XIP) region of the SPI flash memory + * @param size the size of the Execute-in-Place (XIP) region of the SPI flash memory + */ +class WithSPIFlash(address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000, size: BigInt = 0x10000000) extends Config((site, here, up) => { // Note: the default size matches freedom with the addresses below - case PeripherySPIFlashKey => Seq( - SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) + case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq( + SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size)) +}) + +/** + * Config fragment for adding a SPI peripheral device to the SoC + * + * @param address the address of the SPI controller + */ +class WithSPI(address: BigInt = 0x10031000) extends Config((site, here, up) => { + case PeripherySPIKey => up(PeripherySPIKey) ++ Seq( + SPIParams(rAddress = address)) +}) + +/** + * Config fragment for adding a I2C peripheral device to the SoC + * + * @param address the address of the I2C controller + */ +class WithI2C(address: BigInt = 0x10040000) extends Config((site, here, up) => { + case PeripheryI2CKey => up(PeripheryI2CKey) ++ Seq( + I2CParams(address = address, controlXType = AsynchronousCrossing(), intXType = AsynchronousCrossing()) + ) +}) + +class WithNoDebug extends Config((site, here, up) => { + case DebugModuleKey => None }) class WithDMIDTM extends Config((site, here, up) => { case ExportDebug => up(ExportDebug, site).copy(protocols = Set(DMI)) }) -class WithNoDebug extends Config((site, here, up) => { - case DebugModuleKey => None +/** + * Config fragment for adding a JTAG Debug Module to the SoC + * + * @param idcodeVersion the version of the JTAG protocol the Debug Module supports + * @param partNum the part number of the Debug Module + * @param manufId the 11-bit JEDEC Designer ID of the chip manufacturer + * @param debugIdleCycles the number of cycles the Debug Module waits before responding to a request + */ +class WithJTAGDTMKey(idcodeVersion: Int = 2, partNum: Int = 0x000, manufId: Int = 0x489, debugIdleCycles: Int = 5) extends Config((site, here, up) => { + case JtagDTMKey => new JtagDTMConfig ( + idcodeVersion = idcodeVersion, + idcodePartNum = partNum, + idcodeManufId = manufId, + debugIdleCycles = debugIdleCycles) }) class WithTLBackingMemory extends Config((site, here, up) => { From 0de74215a120613ed8e7be439e3d4ebc2adf5d33 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 19 Jun 2023 05:03:59 -0700 Subject: [PATCH 2/7] Restore original default parameter order for WithUART/WithSPIFlash --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 290e3dfe..a2ea2bd9 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -63,7 +63,7 @@ class WithNoUART extends Config((site, here, up) => { * @param address the address of the UART device * @param baudrate the baudrate of the UART device */ -class WithUART(address: BigInt = 0x10020000, baudrate: BigInt = 115200) extends Config ((site, here, up) => { +class WithUART(baudrate: BigInt = 115200, address: BigInt = 0x10020000) extends Config ((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey) ++ Seq( UARTParams(address = address, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate)) }) @@ -79,7 +79,7 @@ class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, * @param fAddress the address of the Execute-in-Place (XIP) region of the SPI flash memory * @param size the size of the Execute-in-Place (XIP) region of the SPI flash memory */ -class WithSPIFlash(address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000, size: BigInt = 0x10000000) extends Config((site, here, up) => { +class WithSPIFlash(size: BigInt = 0x10000000, address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000) extends Config((site, here, up) => { // Note: the default size matches freedom with the addresses below case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq( SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size)) From 563897ba22e22ffad35c45c9aa7ecc710e8e444b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 15 Jun 2023 10:20:52 -0700 Subject: [PATCH 3/7] Add WithUARTInitBaud/fix firesim uart configs --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 4 ++++ generators/firechip/src/main/scala/TargetConfigs.scala | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index a2ea2bd9..9d1a1902 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -72,6 +72,10 @@ class WithUARTFIFOEntries(txEntries: Int, rxEntries: Int) extends Config((site, case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(nTxEntries = txEntries, nRxEntries = rxEntries)) }) +class WithUARTInitBaudRate(baudrate: BigInt = 115200) extends Config ((site, here, up) => { + case PeripheryUARTKey => up(PeripheryUARTKey).map(_.copy(initBaudRate=baudrate)) +}) + /** * Config fragment for adding a SPI peripheral device with Execute-in-Place capability to the SoC * diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 1c821294..dd8cd338 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -92,7 +92,7 @@ class WithFireSimDesignTweaks extends Config( // Optional: reduce the width of the Serial TL interface new testchipip.WithSerialTLWidth(4) ++ // Required*: Scale default baud rate with periphery bus frequency - new chipyard.config.WithUART(BigInt(3686400L)) ++ + new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ // Optional: Adds IO to attach tracerV bridges new chipyard.config.WithTraceIO ++ // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1) @@ -241,7 +241,7 @@ class FireSimSmallSystemConfig extends Config( new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++ new testchipip.WithDefaultSerialTL ++ new testchipip.WithBlockDevice ++ - new chipyard.config.WithUART ++ + new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++ new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++ new chipyard.RocketConfig) From 0da0361a7114e1078354a2517f0f831e70ad3cdf Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 14 Jun 2023 18:37:37 -0700 Subject: [PATCH 4/7] Fix broken docs link --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 9d1a1902..5f6f8571 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -39,6 +39,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = )) }) +// DOC include start: gpio config fragment /** * Config fragment for adding a GPIO peripheral device to the SoC * @@ -49,6 +50,7 @@ class WithGPIO(address: BigInt = 0x10010000, width: Int = 4) extends Config ((si case PeripheryGPIOKey => up(PeripheryGPIOKey) ++ Seq( GPIOParams(address = address, width = width, includeIOF = false)) }) +// DOC include end: gpio config fragment /** * Config fragment for removing all UART peripheral devices from the SoC From 879e13388b7a95c3b55f4890985964475fd34521 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 20 Jun 2023 10:24:48 -0700 Subject: [PATCH 5/7] Fix default WithSPIFlash tests --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 5f6f8571..9bd2ceb2 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -85,7 +85,7 @@ class WithUARTInitBaudRate(baudrate: BigInt = 115200) extends Config ((site, her * @param fAddress the address of the Execute-in-Place (XIP) region of the SPI flash memory * @param size the size of the Execute-in-Place (XIP) region of the SPI flash memory */ -class WithSPIFlash(size: BigInt = 0x10000000, address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000) extends Config((site, here, up) => { +class WithSPIFlash(size: BigInt = 0x10000000, address: BigInt = 0x10040000, fAddress: BigInt = 0x20000000) extends Config((site, here, up) => { // Note: the default size matches freedom with the addresses below case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq( SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size)) From 76948b6d0bf68d7d44fcc4c187d79824b9ce91df Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 20 Jun 2023 15:19:01 -0700 Subject: [PATCH 6/7] FIX: fix SPI Flash base address in test --- tests/spiflash.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/spiflash.h b/tests/spiflash.h index 94b27e36..830302c7 100644 --- a/tests/spiflash.h +++ b/tests/spiflash.h @@ -5,7 +5,7 @@ #define SPIFLASH_BASE_MEM 0x20000000 #define SPIFLASH_BASE_MEM_SIZE 0x10000000 -#define SPIFLASH_BASE_CTRL 0x10040000 +#define SPIFLASH_BASE_CTRL 0x10030000 // Only defining the registers we use; there are more // Software control #define SPIFLASH_OFFS_CSMODE 0x18 From cbce5ffa5610419e50b48347da83ba28cc9302e6 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Tue, 20 Jun 2023 15:20:19 -0700 Subject: [PATCH 7/7] FIX: fix SPI Flash base address Change to match the standardized memory map suggested [here](https://docs.google.com/presentation/d/18qrFsHImYO4OJEpl8oQ_g3m2dc6a2Q0LppnVxTX-19I/edit#slide=id.g1c27f282ad8_0_54) --- .../src/main/scala/config/fragments/PeripheralFragments.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 9bd2ceb2..5f6f8571 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -85,7 +85,7 @@ class WithUARTInitBaudRate(baudrate: BigInt = 115200) extends Config ((site, her * @param fAddress the address of the Execute-in-Place (XIP) region of the SPI flash memory * @param size the size of the Execute-in-Place (XIP) region of the SPI flash memory */ -class WithSPIFlash(size: BigInt = 0x10000000, address: BigInt = 0x10040000, fAddress: BigInt = 0x20000000) extends Config((site, here, up) => { +class WithSPIFlash(size: BigInt = 0x10000000, address: BigInt = 0x10030000, fAddress: BigInt = 0x20000000) extends Config((site, here, up) => { // Note: the default size matches freedom with the addresses below case PeripherySPIFlashKey => up(PeripherySPIFlashKey) ++ Seq( SPIFlashParams(rAddress = address, fAddress = fAddress, fSize = size))