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Fixed BootROM | Updated HarnessBinders

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This commit is contained in:
Abraham Gonzalez
2020-10-26 18:15:58 -07:00
parent a07369acaf
commit 3c42e2cae7
8 changed files with 43 additions and 29 deletions
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13
fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
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@@ -1,7 +1,7 @@
package chipyard.fpga.vcu118.bringup
import chisel3._
import chisel3.experimental.{Analog, IO}
import chisel3.experimental.{Analog, IO, BaseModule}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters, Field}
@@ -19,13 +19,12 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio._
import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer}
import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences}
import chipyard.harness._
/*** UART ***/
class WithBringupUART extends OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
(system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 2)
@@ -39,7 +38,7 @@ class WithBringupUART extends OverrideHarnessBinder({
/*** SPI ***/
class WithBringupSPI extends OverrideHarnessBinder({
(system: HasPeripherySPIModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
(system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 2)
@@ -53,7 +52,7 @@ class WithBringupSPI extends OverrideHarnessBinder({
/*** I2C ***/
class WithBringupI2C extends OverrideHarnessBinder({
(system: HasPeripheryI2CModuleImp, th: HasHarnessSignalReferences, ports: Seq[I2CPort]) => {
(system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 1)
@@ -66,7 +65,7 @@ class WithBringupI2C extends OverrideHarnessBinder({
/*** GPIO ***/
class WithBringupGPIO extends OverrideHarnessBinder({
(system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => {
(system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
(vcu118th.outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) =>
bb_io.bundle <> dut_io
@@ -79,7 +78,7 @@ class WithBringupGPIO extends OverrideHarnessBinder({
/*** Experimental DDR ***/
class WithBringupDDR extends OverrideHarnessBinder({
(system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
(system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
require(ports.size == 1)