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minor fixes to links | misc cleanup

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Abraham Gonzalez
2019-05-27 17:11:10 -07:00
parent 0f34247378
commit 3b14ac8706
7 changed files with 27 additions and 6 deletions
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docs/Tools/Chisel.rst
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@@ -16,4 +16,4 @@ However, if that passes, the output of the generator gives you an FIRRTL file an
See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog.
For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp <https://github.com/freechipsproject/chisel-bootcamp>`__.
Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <>`__.
Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel.eecs.berkeley.edu/>`__.