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Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support

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This commit is contained in:
abejgonzalez
2020-11-05 11:08:36 -08:00
parent c619df2c00 895dcd6831
commit 3994bcecdf
9 changed files with 203 additions and 501 deletions
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69
fpga/src/main/scala/arty/TestHarness.scala
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@@ -1,34 +1,35 @@
//package chipyard.fpga.arty
//
//import chisel3._
//import chisel3.experimental.{Analog}
//
//import freechips.rocketchip.diplomacy.{LazyModule}
//import freechips.rocketchip.config.{Parameters}
//
//import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
//
//import chipyard.{BuildTop, HasHarnessSignalReferences}
//
//class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
//
// val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
//
// // turn IO clock into Reset type
// val hReset = Wire(Reset())
// hReset := ck_rst
//
// // default to 32MHz clock
// withClockAndReset(clock_32MHz, hReset) {
// val dut = Module(ldut.module)
// }
//
// val harnessClock = clock_32MHz
// val harnessReset = hReset
// val success = false.B
// val dutReset = hReset
//
// // must be after HasHarnessSignalReferences assignments
// ldut.harnessFunctions.foreach(_(this))
//}
//
package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{Analog}
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Field, Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions}
import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
// turn IO clock into Reset type
val hReset = Wire(Reset())
hReset := ck_rst
// default to 32MHz clock
withClockAndReset(clock_32MHz, hReset) {
val dut = Module(ldut.module)
}
val harnessClock = clock_32MHz
val harnessReset = hReset
val success = false.B
val dutReset = reset_core
// must be after HasHarnessSignalReferences assignments
ldut match { case d: HasTestHarnessFunctions =>
d.harnessFunctions.foreach(_(this))
ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap)
}
}