From 9135cda9597546805ca58fd9aeefb5c273d90593 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Thu, 17 Sep 2020 13:43:28 -0700 Subject: [PATCH 1/9] Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core. --- fpga/src/main/scala/arty/TestHarness.scala | 2 +- fpga/src/main/scala/arty/e300/IOBinders.scala | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 919e5c99..8f0b7143 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -26,7 +26,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell val harnessClock = clock_32MHz val harnessReset = hReset val success = false.B - val dutReset = hReset + val dutReset = reset_core // must be after HasHarnessSignalReferences assignments ldut.harnessFunctions.foreach(_(this)) diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index 8d866619..6cab4b1e 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -56,10 +56,8 @@ class WithE300Connections extends OverrideIOBinder({ val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - // This needs to be de-asserted synchronously to the coreClk. - val async_corerst = system.aon.rsts.corerst - // Add in debug-controlled reset. - system.reset := ResetCatchAndSync(system.clock, async_corerst, 20) + val io_async_corerst = IO(Input(Bool())).suggestName("core_reset") + system.reset := ResetCatchAndSync(system.clock, io_async_corerst, 20) Debug.connectDebugClockAndReset(system.debug, system.clock) //----------------------------------------------------------------------- @@ -186,6 +184,8 @@ class WithE300Connections extends OverrideIOBinder({ val harnessFn = (baseTh: HasHarnessSignalReferences) => { baseTh match { case th: ArtyShell => + io_async_corerst := th.reset_core + //----------------------------------------------------------------------- // Clock divider //----------------------------------------------------------------------- From afc085a5f4e072195726b33d989d1523346adbfb Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sun, 4 Oct 2020 18:13:47 -0700 Subject: [PATCH 2/9] Removed AON block from E300 design. Debug over JTAG still functioning. --- fpga/src/main/scala/arty/e300/Configs.scala | 3 --- fpga/src/main/scala/arty/e300/DigitalTop.scala | 2 -- fpga/src/main/scala/arty/e300/IOBinders.scala | 14 -------------- 3 files changed, 19 deletions(-) diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/e300/Configs.scala index dd9213fc..ee90848e 100644 --- a/fpga/src/main/scala/arty/e300/Configs.scala +++ b/fpga/src/main/scala/arty/e300/Configs.scala @@ -9,7 +9,6 @@ import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ -import sifive.blocks.devices.mockaon._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.pwm._ import sifive.blocks.devices.spi._ @@ -38,8 +37,6 @@ class E300DevKitExtra extends Config((site, here, up) => { UARTParams(address = 0x10023000)) case PeripheryI2CKey => List( I2CParams(address = 0x10016000)) - case PeripheryMockAONKey => - MockAONParams(address = 0x10000000) case DTSTimebase => BigInt(32768) case JtagDTMKey => new JtagDTMConfig ( idcodeVersion = 2, diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/e300/DigitalTop.scala index 1bda2680..f7d4d8e7 100644 --- a/fpga/src/main/scala/arty/e300/DigitalTop.scala +++ b/fpga/src/main/scala/arty/e300/DigitalTop.scala @@ -14,10 +14,8 @@ import chipyard.{DigitalTop, DigitalTopModule} // ------------------------------------ class E300DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.mockaon.HasPeripheryMockAON { override lazy val module = new E300DigitalTopModule(this) } class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l) - with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala index 6cab4b1e..6675c325 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/e300/IOBinders.scala @@ -12,7 +12,6 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.pwm._ import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.mockaon._ import sifive.blocks.devices.jtag._ import sifive.blocks.devices.pinctrl._ @@ -31,7 +30,6 @@ class WithE300Connections extends OverrideIOBinder({ with HasPeripheryDebugModuleImp with HasPeripheryPWMModuleImp with HasPeripherySPIFlashModuleImp - with HasPeripheryMockAONModuleImp with HasPeripheryI2CModuleImp) => { implicit val p: Parameters = GetSystemParameters(system) @@ -52,7 +50,6 @@ class WithE300Connections extends OverrideIOBinder({ val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") - val io_aon = IO(new MockAONWrapperPins()).suggestName("aon") val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") val io_ndreset = IO(Output(Bool())).suggestName("ndreset") @@ -174,7 +171,6 @@ class WithE300Connections extends OverrideIOBinder({ // AON Pads -- direct connection is OK because // EnhancedPin is hard-coded in MockAONPads // and thus there is no .fromPort method. - io_aon <> system.aon.pins //----------------------------------------------------------------------- //----------------------------------------------------------------------- @@ -322,12 +318,6 @@ class WithE300Connections extends OverrideIOBinder({ IOBUF(th.btn_1, io_gpio.pins(30)) IOBUF(th.btn_2, io_gpio.pins(31)) - val iobuf_btn_3 = Module(new IOBUF()) - iobuf_btn_3.io.I := ~io_aon.pmu.dwakeup_n.o.oval - iobuf_btn_3.io.T := ~io_aon.pmu.dwakeup_n.o.oe - attach(th.btn_3, iobuf_btn_3.io.IO) - io_aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & io_aon.pmu.dwakeup_n.o.ie - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX @@ -343,16 +333,12 @@ class WithE300Connections extends OverrideIOBinder({ // Use the LEDs for some more useful debugging things IOBUF(th.led_0, th.ck_rst) IOBUF(th.led_1, th.SRST_n) - IOBUF(th.led_2, io_aon.pmu.dwakeup_n.i.ival) IOBUF(th.led_3, io_gpio.pins(14)) //--------------------------------------------------------------------- // Unconnected inputs //--------------------------------------------------------------------- - io_aon.erst_n.i.ival := ~th.reset_periph - io_aon.lfextclk.i.ival := slow_clock - io_aon.pmu.vddpaden.i.ival := 1.U } Nil From 9664b848e945dc2eda242d7a0309a01a2a5f9ff9 Mon Sep 17 00:00:00 2001 From: dunn Date: Tue, 6 Oct 2020 11:20:27 -0700 Subject: [PATCH 3/9] Pointing common.mk's SOURCE_DIR to subdirectories of fpga, to avoid circular dependency caused by pointing to fpga, which contains generated-src. --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index ee290ddc..dba98751 100644 --- a/common.mk +++ b/common.mk @@ -58,7 +58,7 @@ include $(base_dir)/tools/dromajo/dromajo.mk # Returns a list of files in directory $1 with file extension $2. lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga/fpga-shells fpga/src) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) # This assumes no SBT meta-build sources From a67318928a377c6cf4d8ac8ea6fc7ca48ac71116 Mon Sep 17 00:00:00 2001 From: dunn Date: Wed, 7 Oct 2020 09:02:30 -0700 Subject: [PATCH 4/9] Bumping submodules to upstream dev's commits. --- generators/icenet | 2 +- generators/testchipip | 2 +- sims/firesim | 2 +- tools/barstools | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/icenet b/generators/icenet index 705ca506..277a9080 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 705ca50690383aa589dc560a5e7c152af04c46ad +Subproject commit 277a9080fe92afb25d942f3207252e0ddea1b864 diff --git a/generators/testchipip b/generators/testchipip index 1e7373f6..10351d36 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 1e7373f6398c198e2dee2bcf692917ec2ac21b53 +Subproject commit 10351d36a961d89e6f5ac1177dff0e9f3efb8c0f diff --git a/sims/firesim b/sims/firesim index 05edd6be..801baeb9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 05edd6be8c0464ea53a664a2164d3eba6a7f62aa +Subproject commit 801baeb901c207beb0511311e09ae10e0dbb8b5f diff --git a/tools/barstools b/tools/barstools index aa1c90c4..4a5c75fc 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit aa1c90c4ccb73c2c379550f3296892cc81e8a195 +Subproject commit 4a5c75fcf85f03af858f1d7db04303d4b0733de7 From 252f9c6a121889367f1c86354fab8710be1a37c1 Mon Sep 17 00:00:00 2001 From: dunn Date: Wed, 7 Oct 2020 11:55:16 -0700 Subject: [PATCH 5/9] Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging. --- fpga/src/main/scala/arty/TestHarness.scala | 25 +++++++++++++++---- .../chipyard/src/main/scala/DigitalTop.scala | 3 --- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 8f0b7143..cd327243 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -2,13 +2,25 @@ package chipyard.fpga.arty import chisel3._ import chisel3.experimental.{Analog} - +import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.config.{Parameters} - +import freechips.rocketchip.config.{Field, Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} - import chipyard.{BuildTop, HasHarnessSignalReferences} +import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} + +trait HasTestHarnessFunctions { + val lazySystem: LazyModule + val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]] + val portMap = scala.collection.mutable.Map[String, Seq[Data]]() +} + +trait HasHarnessSignalReferences { + def harnessClock: Clock + def harnessReset: Reset + def dutReset: Reset + def success: Bool +} class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { @@ -29,6 +41,9 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell val dutReset = reset_core // must be after HasHarnessSignalReferences assignments - ldut.harnessFunctions.foreach(_(this)) + ldut match { case d: HasTestHarnessFunctions => + d.harnessFunctions.foreach(_(this)) + ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } } diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 868286eb..c0ac1ff7 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -32,12 +32,9 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with testchipip.CanHaveTraceIOModuleImp - with testchipip.CanHavePeripheryBlockDeviceModuleImp - with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp - with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop From 7d1a1539e6b716e79725974ae9ebe6cace0f07a2 Mon Sep 17 00:00:00 2001 From: dunn Date: Fri, 9 Oct 2020 23:17:36 -0700 Subject: [PATCH 6/9] Initial pass at HarnessBinders for Arty. --- .../main/scala/arty/{e300 => }/Configs.scala | 8 +- .../scala/arty/{e300 => }/DigitalTop.scala | 2 +- fpga/src/main/scala/arty/HarnessBinders.scala | 73 +++++++++++++++++++ .../scala/arty/{e300 => }/IOBinders.scala | 2 +- 4 files changed, 81 insertions(+), 4 deletions(-) rename fpga/src/main/scala/arty/{e300 => }/Configs.scala (92%) rename fpga/src/main/scala/arty/{e300 => }/DigitalTop.scala (94%) create mode 100644 fpga/src/main/scala/arty/HarnessBinders.scala rename fpga/src/main/scala/arty/{e300 => }/IOBinders.scala (99%) diff --git a/fpga/src/main/scala/arty/e300/Configs.scala b/fpga/src/main/scala/arty/Configs.scala similarity index 92% rename from fpga/src/main/scala/arty/e300/Configs.scala rename to fpga/src/main/scala/arty/Configs.scala index ee90848e..e074dd03 100644 --- a/fpga/src/main/scala/arty/e300/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -1,5 +1,5 @@ // See LICENSE for license details. -package chipyard.fpga.arty.e300 +package chipyard.fpga.arty import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ @@ -16,6 +16,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import chipyard.{BuildSystem} +import chipyard.iobinders class E300DevKitExtra extends Config((site, here, up) => { case PeripheryGPIOKey => List( @@ -51,7 +52,10 @@ class WithE300System extends Config((site, here, up) => { class E300ArtyDevKitConfig extends Config( new WithE300System ++ - new WithE300Connections ++ + new chipyard.iobinders.WithDebugIOCells ++ + new chipyard.iobinders.WithUARTIOCells ++ + new WithArtyJTAGHarnessBinder ++ + new WithArtyUARTHarnessBinder ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/arty/e300/DigitalTop.scala b/fpga/src/main/scala/arty/DigitalTop.scala similarity index 94% rename from fpga/src/main/scala/arty/e300/DigitalTop.scala rename to fpga/src/main/scala/arty/DigitalTop.scala index f7d4d8e7..858b6215 100644 --- a/fpga/src/main/scala/arty/e300/DigitalTop.scala +++ b/fpga/src/main/scala/arty/DigitalTop.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.arty.e300 +package chipyard.fpga.arty import chisel3._ diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala new file mode 100644 index 00000000..0d9a8399 --- /dev/null +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -0,0 +1,73 @@ +package chipyard.fpga.arty + +import chisel3._ +import chisel3.experimental.{Analog} + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters} +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.jtag.{JTAGIO} +import freechips.rocketchip.system.{SimAXIMem} +import freechips.rocketchip.subsystem._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ + +import barstools.iocell.chisel._ + +import testchipip._ + +import chipyard.harness.OverrideHarnessBinder +import chipyard.HasHarnessSignalReferences +import chipyard.iobinders.GetSystemParameters + +import tracegen.{TraceGenSystemModuleImp} +import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} + +import scala.reflect.{ClassTag} + +import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} + + + +class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ + (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + ports.map { + case d: ClockedDMIIO => + // Want to error here. + case j: JTAGIO => + //val dtm_success = WireInit(false.B) + //when (dtm_success) { th.success := true.B } + //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) + + j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt + + IOBUF(th.jd_5, j.TMS) + PULLUP(th.jd_5) + + IOBUF(th.jd_4, j.TDI) + PULLUP(th.jd_4) + + IOBUF(th.jd_0, j.TDO) + + // mimic putting a pullup on this line (part of reset vote) + th.SRST_n := IOBUF(th.jd_6) + PULLUP(th.jd_6) + + IOBUF(th.jd_1, j.TRSTn) + PULLUP(th.jd_1) + } + Nil + } +}) + +class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ + (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { + //UARTAdapter.connect(ports)(system.p) + IOBUF(th.ck_io(2), ports.txd) + IOBUF(th.ck_io(3), ports.rxd) + Nil + } +}) \ No newline at end of file diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala similarity index 99% rename from fpga/src/main/scala/arty/e300/IOBinders.scala rename to fpga/src/main/scala/arty/IOBinders.scala index 6675c325..2b4b332b 100644 --- a/fpga/src/main/scala/arty/e300/IOBinders.scala +++ b/fpga/src/main/scala/arty/IOBinders.scala @@ -1,4 +1,4 @@ -package chipyard.fpga.arty.e300 +package chipyard.fpga.arty import chisel3._ import chisel3.experimental.{attach, IO} From 54acfe71fce0983c9760b7bead421292767f96c0 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sat, 10 Oct 2020 13:45:27 -0700 Subject: [PATCH 7/9] Some HarnessBinder testing with Jerry's debug suggestions. --- fpga/src/main/scala/arty/HarnessBinders.scala | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 0d9a8399..4ee847a5 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -30,44 +30,44 @@ import scala.reflect.{ClassTag} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - - class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { - ports.map { - case d: ClockedDMIIO => - // Want to error here. - case j: JTAGIO => - //val dtm_success = WireInit(false.B) - //when (dtm_success) { th.success := true.B } - //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) + (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[JTAGIO]) => { + // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { + // ports.map { + // case d: ClockedDMIIO => + // // Want to error here. + // case j: JTAGIO => + // //val dtm_success = WireInit(false.B) + // //when (dtm_success) { th.success := true.B } + // //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success) - j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt + // j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt - IOBUF(th.jd_5, j.TMS) - PULLUP(th.jd_5) + // IOBUF(th.jd_5, j.TMS) + // PULLUP(th.jd_5) - IOBUF(th.jd_4, j.TDI) - PULLUP(th.jd_4) + // IOBUF(th.jd_4, j.TDI) + // PULLUP(th.jd_4) - IOBUF(th.jd_0, j.TDO) + // IOBUF(th.jd_0, j.TDO) - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) + // // mimic putting a pullup on this line (part of reset vote) + // th.SRST_n := IOBUF(th.jd_6) + // PULLUP(th.jd_6) - IOBUF(th.jd_1, j.TRSTn) - PULLUP(th.jd_1) - } + // IOBUF(th.jd_1, j.TRSTn) + // PULLUP(th.jd_1) + // } Nil } }) class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { - //UARTAdapter.connect(ports)(system.p) - IOBUF(th.ck_io(2), ports.txd) - IOBUF(th.ck_io(3), ports.rxd) + (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { + // UARTAdapter.connect(ports)(system.p) + // IOBUF(th.ck_io(2), ports.txd) + // IOBUF(th.ck_io(3), ports.rxd) Nil } }) \ No newline at end of file From dca56cd858f5f7b4e7e17e531833b50de6480e72 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sat, 10 Oct 2020 19:55:02 -0700 Subject: [PATCH 8/9] Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala. --- fpga/src/main/scala/arty/Configs.scala | 4 +- fpga/src/main/scala/arty/HarnessBinders.scala | 4 +- fpga/src/main/scala/arty/IOBinders.scala | 351 ------------------ fpga/src/main/scala/arty/TestHarness.scala | 15 +- 4 files changed, 5 insertions(+), 369 deletions(-) delete mode 100644 fpga/src/main/scala/arty/IOBinders.scala diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index e074dd03..e96bcd9c 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -52,10 +52,10 @@ class WithE300System extends Config((site, here, up) => { class E300ArtyDevKitConfig extends Config( new WithE300System ++ - new chipyard.iobinders.WithDebugIOCells ++ - new chipyard.iobinders.WithUARTIOCells ++ new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ + new chipyard.iobinders.WithDebugIOCells ++ + new chipyard.iobinders.WithUARTIOCells ++ new E300DevKitExtra ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 4ee847a5..3dd380ea 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -31,7 +31,7 @@ import scala.reflect.{ClassTag} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryDebugModuleImp, th: HasHarnessSignalReferences, ports: Seq[JTAGIO]) => { + (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => { // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { // ports.map { // case d: ClockedDMIIO => @@ -63,7 +63,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ }) class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // UARTAdapter.connect(ports)(system.p) // IOBUF(th.ck_io(2), ports.txd) diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala deleted file mode 100644 index 2b4b332b..00000000 --- a/fpga/src/main/scala/arty/IOBinders.scala +++ /dev/null @@ -1,351 +0,0 @@ -package chipyard.fpga.arty - -import chisel3._ -import chisel3.experimental.{attach, IO} - -import freechips.rocketchip.util._ -import freechips.rocketchip.devices.debug._ -import freechips.rocketchip.subsystem.{NExtTopInterrupts} - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.pwm._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.jtag._ -import sifive.blocks.devices.pinctrl._ - -import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} - -import chipsalliance.rocketchip.config._ - -import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters} -import chipyard.{HasHarnessSignalReferences} - -class WithE300Connections extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp - with HasPeripheryUARTModuleImp - with HasPeripherySPIModuleImp - with HasPeripheryDebugModuleImp - with HasPeripheryPWMModuleImp - with HasPeripherySPIFlashModuleImp - with HasPeripheryI2CModuleImp) => { - - implicit val p: Parameters = GetSystemParameters(system) - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // E300DigitalTop <-> ChipTop connections - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - - object PinGen { - def apply(): BasePin = { - val pin = new BasePin() - pin - } - } - - val io_jtag = IO(new JTAGPins(() => PinGen(), false)).suggestName("jtag") - val io_gpio = IO(new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))).suggestName("gpio") - val io_qspi = IO(new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))).suggestName("qspi") - val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset") - val io_ndreset = IO(Output(Bool())).suggestName("ndreset") - - val io_async_corerst = IO(Input(Bool())).suggestName("core_reset") - system.reset := ResetCatchAndSync(system.clock, io_async_corerst, 20) - Debug.connectDebugClockAndReset(system.debug, system.clock) - - //----------------------------------------------------------------------- - // Check for unsupported rocket-chip connections - //----------------------------------------------------------------------- - - require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported"); - - //----------------------------------------------------------------------- - // Build GPIO Pin Mux - //----------------------------------------------------------------------- - // Pin Mux for UART, SPI, PWM - // First convert the System outputs into "IOF" using the respective *GPIOPort - // converters. - - val sys_uart = system.uart - val sys_pwm = system.pwm - val sys_spi = system.spi - val sys_i2c = system.i2c - - val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))} - val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))} - val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))} - val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))} - - (uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) } - (spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - (i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = system.clock, reset = system.reset.asBool, syncStages = 0)} - - //----------------------------------------------------------------------- - // Default Pin connections before attaching pinmux - - for (iof_0 <- system.gpio(0).iof_0.get) { - iof_0.default() - } - - for (iof_1 <- system.gpio(0).iof_1.get) { - iof_1.default() - } - - //----------------------------------------------------------------------- - - val iof_0 = system.gpio(0).iof_0.get - val iof_1 = system.gpio(0).iof_1.get - - // SPI1 (0 is the dedicated) - BasePinToIOF(spi_pins(0).cs(0), iof_0(2)) - BasePinToIOF(spi_pins(0).dq(0), iof_0(3)) - BasePinToIOF(spi_pins(0).dq(1), iof_0(4)) - BasePinToIOF(spi_pins(0).sck, iof_0(5)) - BasePinToIOF(spi_pins(0).dq(2), iof_0(6)) - BasePinToIOF(spi_pins(0).dq(3), iof_0(7)) - BasePinToIOF(spi_pins(0).cs(1), iof_0(8)) - BasePinToIOF(spi_pins(0).cs(2), iof_0(9)) - BasePinToIOF(spi_pins(0).cs(3), iof_0(10)) - - // SPI2 - BasePinToIOF(spi_pins(1).cs(0), iof_0(26)) - BasePinToIOF(spi_pins(1).dq(0), iof_0(27)) - BasePinToIOF(spi_pins(1).dq(1), iof_0(28)) - BasePinToIOF(spi_pins(1).sck, iof_0(29)) - BasePinToIOF(spi_pins(1).dq(2), iof_0(30)) - BasePinToIOF(spi_pins(1).dq(3), iof_0(31)) - - // I2C - if (p(PeripheryI2CKey).length == 1) { - BasePinToIOF(i2c_pins(0).sda, iof_0(12)) - BasePinToIOF(i2c_pins(0).scl, iof_0(13)) - } - - // UART0 - BasePinToIOF(uart_pins(0).rxd, iof_0(16)) - BasePinToIOF(uart_pins(0).txd, iof_0(17)) - - // UART1 - BasePinToIOF(uart_pins(1).rxd, iof_0(24)) - BasePinToIOF(uart_pins(1).txd, iof_0(25)) - - //PWM - BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) ) - BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) ) - BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) ) - BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) ) - - BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19)) - BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20)) - BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21)) - BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22)) - - BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10)) - BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11)) - BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12)) - BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13)) - - //----------------------------------------------------------------------- - // Drive actual Pads - //----------------------------------------------------------------------- - - // Result of Pin Mux - GPIOPinsFromPort(io_gpio, system.gpio(0)) - - // Dedicated SPI Pads - SPIPinsFromPort(io_qspi, system.qspi(0), clock = system.clock, reset = system.reset.asBool, syncStages = 3) - - // JTAG Debug Interface - val sjtag = system.debug.get.systemjtag.get - JTAGPinsFromPort(io_jtag, sjtag.jtag) - sjtag.reset := io_jtag_reset - sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) - - io_ndreset := system.debug.get.ndreset - - // AON Pads -- direct connection is OK because - // EnhancedPin is hard-coded in MockAONPads - // and thus there is no .fromPort method. - - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - // Harness Function (ArtyHarness <-> ChipTop) - //----------------------------------------------------------------------- - //----------------------------------------------------------------------- - val harnessFn = (baseTh: HasHarnessSignalReferences) => { - baseTh match { case th: ArtyShell => - - io_async_corerst := th.reset_core - - //----------------------------------------------------------------------- - // Clock divider - //----------------------------------------------------------------------- - val slow_clock = Wire(Bool()) - - // Divide clock by 256, used to generate 32.768 kHz clock for AON block - withClockAndReset(th.clock_8MHz, ~th.mmcm_locked) { - val clockToggleReg = RegInit(false.B) - val (_, slowTick) = chisel3.util.Counter(true.B, 256) - when (slowTick) {clockToggleReg := ~clockToggleReg} - slow_clock := clockToggleReg - } - - //----------------------------------------------------------------------- - // DUT - //----------------------------------------------------------------------- - withClockAndReset(th.clock_32MHz, th.ck_rst) { - - //--------------------------------------------------------------------- - // SPI flash IOBUFs - //--------------------------------------------------------------------- - - IOBUF(th.qspi_sck, io_qspi.sck) - IOBUF(th.qspi_cs, io_qspi.cs(0)) - - IOBUF(th.qspi_dq(0), io_qspi.dq(0)) - IOBUF(th.qspi_dq(1), io_qspi.dq(1)) - IOBUF(th.qspi_dq(2), io_qspi.dq(2)) - IOBUF(th.qspi_dq(3), io_qspi.dq(3)) - - //--------------------------------------------------------------------- - // JTAG IOBUFs - //--------------------------------------------------------------------- - - io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt - - IOBUF(th.jd_5, io_jtag.TMS) - PULLUP(th.jd_5) - - IOBUF(th.jd_4, io_jtag.TDI) - PULLUP(th.jd_4) - - IOBUF(th.jd_0, io_jtag.TDO) - - // mimic putting a pullup on this line (part of reset vote) - th.SRST_n := IOBUF(th.jd_6) - PULLUP(th.jd_6) - - // jtag reset - val jtag_power_on_reset = PowerOnResetFPGAOnly(th.clock_32MHz) - io_jtag_reset := jtag_power_on_reset - - // debug reset - th.dut_ndreset := io_ndreset - - //--------------------------------------------------------------------- - // Assignment to package pins - //--------------------------------------------------------------------- - // Pins IO0-IO13 - // - // FTDI UART TX/RX are not connected to th.ck_io[0,1] - // the way they are on Arduino boards. We copy outgoing - // data to both places, switch 3 (sw[3]) determines whether - // input to UART comes from FTDI chip or gpio_16 (shield pin PD0) - - val iobuf_ck0 = Module(new IOBUF()) - iobuf_ck0.io.I := io_gpio.pins(16).o.oval - iobuf_ck0.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_ck0.io.IO, th.ck_io(0)) // UART0 RX - - val iobuf_uart_txd = Module(new IOBUF()) - iobuf_uart_txd.io.I := io_gpio.pins(16).o.oval - iobuf_uart_txd.io.T := ~io_gpio.pins(16).o.oe - attach(iobuf_uart_txd.io.IO, th.uart_txd_in) - - // gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3] - val sw_3_in = IOBUF(th.sw_3) - io_gpio.pins(16).i.ival := Mux(sw_3_in, - iobuf_ck0.io.O & io_gpio.pins(16).o.ie, - iobuf_uart_txd.io.O & io_gpio.pins(16).o.ie) - - IOBUF(th.uart_rxd_out, io_gpio.pins(17)) - - // Shield header row 0: PD2-PD7 - IOBUF(th.ck_io(2), io_gpio.pins(18)) - IOBUF(th.ck_io(3), io_gpio.pins(19)) // PWM1(1) - IOBUF(th.ck_io(4), io_gpio.pins(20)) // PWM1(0) - IOBUF(th.ck_io(5), io_gpio.pins(21)) // PWM1(2) - IOBUF(th.ck_io(6), io_gpio.pins(22)) // PWM1(3) - IOBUF(th.ck_io(7), io_gpio.pins(23)) - - // Header row 1: PB0-PB5 - IOBUF(th.ck_io(8), io_gpio.pins(0)) // PWM0(0) - IOBUF(th.ck_io(9), io_gpio.pins(1)) // PWM0(1) - IOBUF(th.ck_io(10), io_gpio.pins(2)) // SPI CS(0) / PWM0(2) - IOBUF(th.ck_io(11), io_gpio.pins(3)) // SPI MOSI / PWM0(3) - IOBUF(th.ck_io(12), io_gpio.pins(4)) // SPI MISO - IOBUF(th.ck_io(13), io_gpio.pins(5)) // SPI SCK - - io_gpio.pins(6).i.ival := 0.U - io_gpio.pins(7).i.ival := 0.U - io_gpio.pins(8).i.ival := 0.U - - // Header row 3: A0-A5 (we don't support using them as analog inputs) - // just treat them as regular digital GPIOs - IOBUF(th.ck_io(15), io_gpio.pins(9)) // A1 = CS(2) - IOBUF(th.ck_io(16), io_gpio.pins(10)) // A2 = CS(3) / PWM2(0) - IOBUF(th.ck_io(17), io_gpio.pins(11)) // A3 = PWM2(1) - IOBUF(th.ck_io(18), io_gpio.pins(12)) // A4 = PWM2(2) / SDA - IOBUF(th.ck_io(19), io_gpio.pins(13)) // A5 = PWM2(3) / SCL - - // Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty - // assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active - IOBUF(th.led0_r, io_gpio.pins(1)) - IOBUF(th.led0_g, io_gpio.pins(2)) - IOBUF(th.led0_b, io_gpio.pins(3)) - - // Note that this is the one which is actually connected on the HiFive/Crazy88 - // Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active - IOBUF(th.led1_r, io_gpio.pins(19)) - IOBUF(th.led1_g, io_gpio.pins(21)) - IOBUF(th.led1_b, io_gpio.pins(22)) - - // and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active - IOBUF(th.led2_r, io_gpio.pins(11)) - IOBUF(th.led2_g, io_gpio.pins(12)) - IOBUF(th.led2_b, io_gpio.pins(13)) - - // Only 19 out of 20 shield pins connected to GPIO pins - // Shield pin A5 (pin 14) left unconnected - // The buttons are connected to some extra GPIO pins not connected on the - // HiFive1 board - IOBUF(th.btn_0, io_gpio.pins(15)) - IOBUF(th.btn_1, io_gpio.pins(30)) - IOBUF(th.btn_2, io_gpio.pins(31)) - - // UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1 - IOBUF(th.ja_0, io_gpio.pins(25)) // UART1 TX - IOBUF(th.ja_1, io_gpio.pins(24)) // UART1 RX - - // SPI2 pins mapped to 6 pin ICSP connector (standard on later - // arduinos) These are connected to some extra GPIO pins not connected - // on the HiFive1 board - IOBUF(th.ck_ss, io_gpio.pins(26)) - IOBUF(th.ck_mosi, io_gpio.pins(27)) - IOBUF(th.ck_miso, io_gpio.pins(28)) - IOBUF(th.ck_sck, io_gpio.pins(29)) - - // Use the LEDs for some more useful debugging things - IOBUF(th.led_0, th.ck_rst) - IOBUF(th.led_1, th.SRST_n) - IOBUF(th.led_3, io_gpio.pins(14)) - - //--------------------------------------------------------------------- - // Unconnected inputs - //--------------------------------------------------------------------- - - } - - Nil - } - } - - Seq((Nil, Nil, Some(harnessFn))) - } -}) - diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index cd327243..76dc6a3c 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -6,22 +6,9 @@ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} -import chipyard.{BuildTop, HasHarnessSignalReferences} +import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions} import chipyard.harness.{ApplyHarnessBinders, HarnessBinders} -trait HasTestHarnessFunctions { - val lazySystem: LazyModule - val harnessFunctions = ArrayBuffer.empty[HasHarnessSignalReferences => Seq[Any]] - val portMap = scala.collection.mutable.Map[String, Seq[Data]]() -} - -trait HasHarnessSignalReferences { - def harnessClock: Clock - def harnessReset: Reset - def dutReset: Reset - def success: Bool -} - class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences { val ldut = LazyModule(p(BuildTop)(p)).suggestName("chiptop") From 895dcd6831c7fbcfaf74da5a080c45f0a6ebe55d Mon Sep 17 00:00:00 2001 From: James Dunn Date: Sun, 11 Oct 2020 11:12:33 -0700 Subject: [PATCH 9/9] referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue. --- fpga/src/main/scala/arty/HarnessBinders.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 3dd380ea..89105d78 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -30,7 +30,7 @@ import scala.reflect.{ClassTag} import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly} -class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ +class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => { // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => { // ports.map { @@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ } }) -class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ +class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { // UARTAdapter.connect(ports)(system.p) @@ -70,4 +70,4 @@ class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ // IOBUF(th.ck_io(3), ports.rxd) Nil } -}) \ No newline at end of file +})