Switch RTL-sim/FPGA/VLSI flows to chisel6

2024-04-23 11:48:33 -07:00
parent daf4b64f52
commit 39092e9b00
4 changed files with 45 additions and 23 deletions
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -45,6 +45,7 @@ VLSI_TOP           ?= $(TOP)
 VLSI_MODEL_DUT_NAME ?= chiptop0
 # If overriding, this should be relative to $(vlsi_dir)
 VLSI_OBJ_DIR       ?= build
+export USE_CHISEL6        = 1
 ifneq ($(CUSTOM_VLOG),)
 	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(VLSI_TOP)
 else