Switch RTL-sim/FPGA/VLSI flows to chisel6

2024-04-23 11:48:33 -07:00
parent daf4b64f52
commit 39092e9b00
4 changed files with 45 additions and 23 deletions
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -87,6 +87,8 @@ ifeq ($(SUB_PROJECT),arty100t)
 	FPGA_BRAND        ?= xilinx
 endif

+export USE_CHISEL6=1
+
 include $(base_dir)/variables.mk

 # default variables to build the arty example