From 847f72eca0fa3207ab7140c07e980ac9f8cf1251 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 14 Sep 2020 19:39:44 -0700 Subject: [PATCH 1/2] Support plusarg_reader blackbox in the harness --- tapeout/src/main/scala/transforms/Generate.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tapeout/src/main/scala/transforms/Generate.scala b/tapeout/src/main/scala/transforms/Generate.scala index 89df8b55..3ed105fe 100644 --- a/tapeout/src/main/scala/transforms/Generate.scala +++ b/tapeout/src/main/scala/transforms/Generate.scala @@ -221,7 +221,7 @@ sealed trait GenerateTopAndHarnessApp extends LazyLogging { this: App => // Execute top and get list of ExtModules to avoid collisions val topExtModules = executeTop() - val externals = Seq("SimSerial", "SimDTM") ++ harnessTop ++ synTop + val externals = Seq("SimSerial", "SimDTM", "plusarg_reader") ++ harnessTop ++ synTop val harnessAnnos = tapeoutOptions.harnessDotfOut.map(BlackBoxResourceFileNameAnno(_)).toSeq ++ From 4a5c75fcf85f03af858f1d7db04303d4b0733de7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 17 Sep 2020 13:21:32 -0700 Subject: [PATCH 2/2] Add explicit naming of IOs generated by generateIOFromSignal --- iocell/src/main/scala/chisel/IOCell.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/iocell/src/main/scala/chisel/IOCell.scala b/iocell/src/main/scala/chisel/IOCell.scala index 93dfac2f..a5926030 100644 --- a/iocell/src/main/scala/chisel/IOCell.scala +++ b/iocell/src/main/scala/chisel/IOCell.scala @@ -127,13 +127,13 @@ object IOCell { * AsyncReset, and otherwise to Bool (sync reset) * @return A tuple of (the generated IO data node, a Seq of all generated IO cell instances) */ - def generateIOFromSignal[T <: Data](coreSignal: T, name: Option[String] = None, + def generateIOFromSignal[T <: Data](coreSignal: T, name: String, typeParams: IOCellTypeParams = GenericIOCellParams(), abstractResetAsAsync: Boolean = false): (T, Seq[IOCell]) = { - val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)) + val padSignal = IO(DataMirror.internal.chiselTypeClone[T](coreSignal)).suggestName(name) val resetFn = if (abstractResetAsAsync) toAsyncReset else toSyncReset - val iocells = IOCell.generateFromSignal(coreSignal, padSignal, name, typeParams, resetFn) + val iocells = IOCell.generateFromSignal(coreSignal, padSignal, Some(s"iocell_$name"), typeParams, resetFn) (padSignal, iocells) }